A low-cost SOC debug platform based on on-chip test architectures

While the complexity of System-on-a-Chip (SoC) design keeps growing rapidly today the need for an efficient approach to catch design errors at silicon stage has become an urgent issue. In this paper we present a platform for silicon debugging that makes use of an existing test architecture and thus can provide many powerful debug features while requiring very low extra overhead. It supports multi-core debugging for general purpose cores in an SOC chip with the capabilities of on-line tracing, hardware breakpoint insertion and cycle-based stepping. An automatic design tool is also developed to cooperate with the debug platform. Together users can easily control debug operations and examine trace results to efficiently identify the root cause of failures in the silicon.