{"title":"基于0.18μm CMOS的10Gbps突发模式CDR电路","authors":"Che-Fu Liang, Sy-Chyuan Hwu, Shen-Iuan Liu","doi":"10.1109/CICC.2006.320828","DOIUrl":null,"url":null,"abstract":"A 10Gbps burst-mode clock and data recovery (CDR) circuit has been fabricated in 0.18mum CMOS technology. It recovers the input data and clock within 32 bits by using a gated voltage-controlled oscillator, a quadrature generator and a phase-aligning loop incorporating a half-rate bang-bang phase detector and a digital phase interpolator. The measured peak-to-peak jitter of the recovered clock is 10.44ps. The die area is 1.73 times 2.01 mm2 and draw 200mW from a 1.8V supply.","PeriodicalId":269854,"journal":{"name":"IEEE Custom Integrated Circuits Conference 2006","volume":"30 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2006-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"20","resultStr":"{\"title\":\"A 10Gbps Burst-Mode CDR Circuit in 0.18μm CMOS\",\"authors\":\"Che-Fu Liang, Sy-Chyuan Hwu, Shen-Iuan Liu\",\"doi\":\"10.1109/CICC.2006.320828\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A 10Gbps burst-mode clock and data recovery (CDR) circuit has been fabricated in 0.18mum CMOS technology. It recovers the input data and clock within 32 bits by using a gated voltage-controlled oscillator, a quadrature generator and a phase-aligning loop incorporating a half-rate bang-bang phase detector and a digital phase interpolator. The measured peak-to-peak jitter of the recovered clock is 10.44ps. The die area is 1.73 times 2.01 mm2 and draw 200mW from a 1.8V supply.\",\"PeriodicalId\":269854,\"journal\":{\"name\":\"IEEE Custom Integrated Circuits Conference 2006\",\"volume\":\"30 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2006-09-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"20\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"IEEE Custom Integrated Circuits Conference 2006\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/CICC.2006.320828\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"IEEE Custom Integrated Circuits Conference 2006","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/CICC.2006.320828","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 20
摘要
一个10Gbps突发模式时钟和数据恢复(CDR)电路已制成0.18 μ m CMOS技术。它通过使用一个门控压控振荡器、一个正交发生器和一个包含半速率bang-bang相位检测器和数字相位插补器的相位对准环路来恢复输入数据和32位内的时钟。测量到的恢复时钟的峰对峰抖动为10.44ps。模具面积为1.73乘以2.01 mm2，从1.8V电源吸取200mW。
A 10Gbps burst-mode clock and data recovery (CDR) circuit has been fabricated in 0.18mum CMOS technology. It recovers the input data and clock within 32 bits by using a gated voltage-controlled oscillator, a quadrature generator and a phase-aligning loop incorporating a half-rate bang-bang phase detector and a digital phase interpolator. The measured peak-to-peak jitter of the recovered clock is 10.44ps. The die area is 1.73 times 2.01 mm2 and draw 200mW from a 1.8V supply.
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