Hardware Implementation of Firefly Optimization Algorithm Using FPGAs

Mimicking natural phenomenon of social insects, such as bird flocks and insect colonies by merging randomness facility and some other simulation rules, are the core tasks of the artificial meta-heuristic algorithms. Such algorithms are the most efficient and powerful techniques used to solve various complicated real-world optimization problems. Firefly algorithm, which belongs to nature meta-heuristics algorithms, is inspired by mating and flashing behavior or the phenomenon of bioluminescent communication of fireflies in the nature. In this paper, a hardware structure design for firefly algorithm has been proposed. Firefly algorithm is executing sequentially as all meta-heuristic algorithms, due to the nature of the algorithm. Therefore, sequential hardware structure design for the algorithm using Finite State Machine (FSM) system has been proposed. The hardware design structure implementation is mapped into a FPGAs (SPARTAN 3XS1600) device. Numerical results of the comparison between the hardware and the software (using C++ programming language) implementation of Firefly algorithm were obtained. These results indicate that the hardware implementation is executed 461 times faster than the software implementation. Indeed, the required execution time for finding the optimal solution can be reduced rapidly using the proposed hardware design structure.