{"title":"一个1.5 GBaud/sec串行链路单片芯片组","authors":"B. Lai, R. Walker, C. Stout, Jieh-Tsorng Wu","doi":"10.1109/EUMA.1992.335690","DOIUrl":null,"url":null,"abstract":"A 1.5 GBaud/s serial data link comprised of a 2-chip set capable of transporting up to 21 parallel bits was successfully fabricated using a 25 GHz peak ft silicon bipolar process. This link features a new encoding scheme which allows DC balance in the serial stream, as well as an internally generated clock which phase locks to the user's clock at the transmitter, and full clock recovery and data retiming at the receiver. In addition, a controller integrated with the link handles handshaking at start up for full duplex operation.","PeriodicalId":317106,"journal":{"name":"1992 22nd European Microwave Conference","volume":"49 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1992-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":"{\"title\":\"A 1.5 GBaud/sec Serial Link Monolithic Chip Set\",\"authors\":\"B. Lai, R. Walker, C. Stout, Jieh-Tsorng Wu\",\"doi\":\"10.1109/EUMA.1992.335690\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A 1.5 GBaud/s serial data link comprised of a 2-chip set capable of transporting up to 21 parallel bits was successfully fabricated using a 25 GHz peak ft silicon bipolar process. This link features a new encoding scheme which allows DC balance in the serial stream, as well as an internally generated clock which phase locks to the user's clock at the transmitter, and full clock recovery and data retiming at the receiver. In addition, a controller integrated with the link handles handshaking at start up for full duplex operation.\",\"PeriodicalId\":317106,\"journal\":{\"name\":\"1992 22nd European Microwave Conference\",\"volume\":\"49 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1992-10-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"2\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"1992 22nd European Microwave Conference\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/EUMA.1992.335690\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"1992 22nd European Microwave Conference","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/EUMA.1992.335690","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A 1.5 GBaud/s serial data link comprised of a 2-chip set capable of transporting up to 21 parallel bits was successfully fabricated using a 25 GHz peak ft silicon bipolar process. This link features a new encoding scheme which allows DC balance in the serial stream, as well as an internally generated clock which phase locks to the user's clock at the transmitter, and full clock recovery and data retiming at the receiver. In addition, a controller integrated with the link handles handshaking at start up for full duplex operation.