基于规范的ARM VMSAv8-64内存管理单元测试程序生成

M. Chupilko, A. Kamkin, A. Kotsynyak, Alexander Protsenko, S. Smolov, A. Tatarnikov
{"title":"基于规范的ARM VMSAv8-64内存管理单元测试程序生成","authors":"M. Chupilko, A. Kamkin, A. Kotsynyak, Alexander Protsenko, S. Smolov, A. Tatarnikov","doi":"10.1109/MTV.2015.13","DOIUrl":null,"url":null,"abstract":"In this paper, a tool for automatically generating test programs for ARM VMSAv8-64 memory management units is described. The solution is based on the MicroTESK framework being developed at ISP RAS. The tool consists of two parts: an architecture-independent test program generation core and VMSAv8-64 specifications. Such separation is not a new principle in the area -- it is applied in a number of industrial test program generators, including IBM's Genesys-Pro. The main distinction is in how specifications are represented, what sort of information is extracted from them, and how that information is exploited. In the suggested approach, specifications comprise descriptions of the memory access instructions, loads and stores, and definition of the memory management mechanisms such as translation lookaside buffers, page tables, and cache units. The tool analyzes the specifications and extracts the execution paths and inter-path dependencies. The extracted information is used to systematically enumerate test programs for a given user-defined template. Test data for a particular program are generated by using symbolic execution and constraint solving techniques.","PeriodicalId":273432,"journal":{"name":"2015 16th International Workshop on Microprocessor and SOC Test and Verification (MTV)","volume":"118 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2015-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"8","resultStr":"{\"title\":\"Specification-Based Test Program Generation for ARM VMSAv8-64 Memory Management Units\",\"authors\":\"M. Chupilko, A. Kamkin, A. Kotsynyak, Alexander Protsenko, S. Smolov, A. Tatarnikov\",\"doi\":\"10.1109/MTV.2015.13\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"In this paper, a tool for automatically generating test programs for ARM VMSAv8-64 memory management units is described. The solution is based on the MicroTESK framework being developed at ISP RAS. The tool consists of two parts: an architecture-independent test program generation core and VMSAv8-64 specifications. Such separation is not a new principle in the area -- it is applied in a number of industrial test program generators, including IBM's Genesys-Pro. The main distinction is in how specifications are represented, what sort of information is extracted from them, and how that information is exploited. In the suggested approach, specifications comprise descriptions of the memory access instructions, loads and stores, and definition of the memory management mechanisms such as translation lookaside buffers, page tables, and cache units. The tool analyzes the specifications and extracts the execution paths and inter-path dependencies. The extracted information is used to systematically enumerate test programs for a given user-defined template. Test data for a particular program are generated by using symbolic execution and constraint solving techniques.\",\"PeriodicalId\":273432,\"journal\":{\"name\":\"2015 16th International Workshop on Microprocessor and SOC Test and Verification (MTV)\",\"volume\":\"118 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2015-12-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"8\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2015 16th International Workshop on Microprocessor and SOC Test and Verification (MTV)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/MTV.2015.13\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2015 16th International Workshop on Microprocessor and SOC Test and Verification (MTV)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/MTV.2015.13","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 8

摘要

本文介绍了一种自动生成ARM VMSAv8-64内存管理单元测试程序的工具。该解决方案基于ISP RAS正在开发的microtask框架。该工具由两部分组成:独立于体系结构的测试程序生成核心和VMSAv8-64规范。这种分离在该领域并不是一个新原理,它已经应用于许多工业测试程序生成器中,包括IBM的genesis - pro。主要的区别在于如何表示规范,从规范中提取什么类型的信息,以及如何利用这些信息。在建议的方法中,规范包括对内存访问指令、加载和存储的描述,以及内存管理机制的定义,例如翻译暂存缓冲区、页表和缓存单元。该工具分析规范并提取执行路径和路径间依赖项。提取的信息用于系统地枚举给定用户定义模板的测试程序。使用符号执行和约束求解技术生成特定程序的测试数据。
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Specification-Based Test Program Generation for ARM VMSAv8-64 Memory Management Units
In this paper, a tool for automatically generating test programs for ARM VMSAv8-64 memory management units is described. The solution is based on the MicroTESK framework being developed at ISP RAS. The tool consists of two parts: an architecture-independent test program generation core and VMSAv8-64 specifications. Such separation is not a new principle in the area -- it is applied in a number of industrial test program generators, including IBM's Genesys-Pro. The main distinction is in how specifications are represented, what sort of information is extracted from them, and how that information is exploited. In the suggested approach, specifications comprise descriptions of the memory access instructions, loads and stores, and definition of the memory management mechanisms such as translation lookaside buffers, page tables, and cache units. The tool analyzes the specifications and extracts the execution paths and inter-path dependencies. The extracted information is used to systematically enumerate test programs for a given user-defined template. Test data for a particular program are generated by using symbolic execution and constraint solving techniques.
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