{"title":"带单参考频率振荡器的全数字锁相环","authors":"D. Badarov, G. Mihov","doi":"10.1109/ET50336.2020.9238157","DOIUrl":null,"url":null,"abstract":"All-digital Phase Locked Loop is designed in this article. A combinational frequency multiplier is developed and tested to achieve completely integrated system using only one low frequency reference oscillator. Adaptive proportional-integral regulation is used to ensure high stability, low phase noise and fast synchronization in wide frequency range. The system is developed and tested on Spartan 3E FPGA by Xilinx.","PeriodicalId":178356,"journal":{"name":"2020 XXIX International Scientific Conference Electronics (ET)","volume":"2020 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2020-09-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":"{\"title\":\"All-Digital Phase Locked Loop with Single Reference Frequency Oscillator\",\"authors\":\"D. Badarov, G. Mihov\",\"doi\":\"10.1109/ET50336.2020.9238157\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"All-digital Phase Locked Loop is designed in this article. A combinational frequency multiplier is developed and tested to achieve completely integrated system using only one low frequency reference oscillator. Adaptive proportional-integral regulation is used to ensure high stability, low phase noise and fast synchronization in wide frequency range. The system is developed and tested on Spartan 3E FPGA by Xilinx.\",\"PeriodicalId\":178356,\"journal\":{\"name\":\"2020 XXIX International Scientific Conference Electronics (ET)\",\"volume\":\"2020 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2020-09-16\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"1\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2020 XXIX International Scientific Conference Electronics (ET)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ET50336.2020.9238157\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2020 XXIX International Scientific Conference Electronics (ET)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ET50336.2020.9238157","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 1
摘要
本文设计了全数字锁相环。开发并测试了一种组合倍频器，以实现仅使用一个低频参考振荡器的完全集成系统。采用自适应比例积分调节，在宽频率范围内保证高稳定性、低相位噪声和快速同步。该系统在赛灵思公司的Spartan 3E FPGA上进行了开发和测试。
All-Digital Phase Locked Loop with Single Reference Frequency Oscillator
All-digital Phase Locked Loop is designed in this article. A combinational frequency multiplier is developed and tested to achieve completely integrated system using only one low frequency reference oscillator. Adaptive proportional-integral regulation is used to ensure high stability, low phase noise and fast synchronization in wide frequency range. The system is developed and tested on Spartan 3E FPGA by Xilinx.
京公网安备 11010802042870号
京ICP备2023020795号-1
分享
求助内容：
应助结果提醒方式：
扫码关注我们
