低钾有机薄膜中孔型控制铜双大马士革互连的工艺设计方法

K. Kinoshita, M. Tada, T. Usami, M. Hiroi, T. Tonegawa, K. Shiba, T. Onodera, M. Tagami, S. Saitoh, Y. Hayashi
{"title":"低钾有机薄膜中孔型控制铜双大马士革互连的工艺设计方法","authors":"K. Kinoshita, M. Tada, T. Usami, M. Hiroi, T. Tonegawa, K. Shiba, T. Onodera, M. Tagami, S. Saitoh, Y. Hayashi","doi":"10.1109/IEDM.2000.904305","DOIUrl":null,"url":null,"abstract":"By dual hard mask (dHM) process combined with sidewall-hardening etching step, copper dual-damascene (DD) interconnects are fabricated in low-k organic film without any etch-stop layers under the trench. Careful designs of dHM structures and their patterning sequence enable us to harden the via-sidewall by fluorocarbon plasma, which is a key to reduce final via-shoulder loss at the via/trench connecting region. The low-k structure has low via resistance such as 0.65 /spl Omega//0.28 /spl mu/m/sup /spl phi//-via while keeping the large tolerance of misalignment in via/trench, appreciable for 0.1 /spl mu/m-generation CMOS ULSIs.","PeriodicalId":276800,"journal":{"name":"International Electron Devices Meeting 2000. Technical Digest. IEDM (Cat. No.00CH37138)","volume":"218 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2000-12-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"6","resultStr":"{\"title\":\"Process design methodology for via-shape-controlled, copper dual-damascene interconnects in low-k organic film\",\"authors\":\"K. Kinoshita, M. Tada, T. Usami, M. Hiroi, T. Tonegawa, K. Shiba, T. Onodera, M. Tagami, S. Saitoh, Y. Hayashi\",\"doi\":\"10.1109/IEDM.2000.904305\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"By dual hard mask (dHM) process combined with sidewall-hardening etching step, copper dual-damascene (DD) interconnects are fabricated in low-k organic film without any etch-stop layers under the trench. Careful designs of dHM structures and their patterning sequence enable us to harden the via-sidewall by fluorocarbon plasma, which is a key to reduce final via-shoulder loss at the via/trench connecting region. The low-k structure has low via resistance such as 0.65 /spl Omega//0.28 /spl mu/m/sup /spl phi//-via while keeping the large tolerance of misalignment in via/trench, appreciable for 0.1 /spl mu/m-generation CMOS ULSIs.\",\"PeriodicalId\":276800,\"journal\":{\"name\":\"International Electron Devices Meeting 2000. Technical Digest. IEDM (Cat. No.00CH37138)\",\"volume\":\"218 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2000-12-10\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"6\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"International Electron Devices Meeting 2000. Technical Digest. IEDM (Cat. No.00CH37138)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/IEDM.2000.904305\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"International Electron Devices Meeting 2000. Technical Digest. IEDM (Cat. No.00CH37138)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/IEDM.2000.904305","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 6

摘要

采用双硬掩膜(dHM)工艺结合侧壁硬化蚀刻步骤,在低钾有机薄膜中制备了铜双砷(DD)互连,在沟槽下不需要任何刻蚀停止层。dHM结构及其图案顺序的精心设计使我们能够通过氟碳等离子体硬化通孔侧壁,这是减少通孔/沟槽连接区域最终通孔肩损失的关键。低k结构具有0.65 /spl Omega//0.28 /spl mu/m/sup /spl phi//-via等低通孔电阻,同时在通孔/沟槽中保持较大的偏差容限,对于0.1 /spl mu/m一代CMOS ulsi来说非常明显。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
查看原文
分享 分享
微信好友 朋友圈 QQ好友 复制链接
本刊更多论文
Process design methodology for via-shape-controlled, copper dual-damascene interconnects in low-k organic film
By dual hard mask (dHM) process combined with sidewall-hardening etching step, copper dual-damascene (DD) interconnects are fabricated in low-k organic film without any etch-stop layers under the trench. Careful designs of dHM structures and their patterning sequence enable us to harden the via-sidewall by fluorocarbon plasma, which is a key to reduce final via-shoulder loss at the via/trench connecting region. The low-k structure has low via resistance such as 0.65 /spl Omega//0.28 /spl mu/m/sup /spl phi//-via while keeping the large tolerance of misalignment in via/trench, appreciable for 0.1 /spl mu/m-generation CMOS ULSIs.
求助全文
通过发布文献求助,成功后即可免费获取论文全文。 去求助
来源期刊
自引率
0.00%
发文量
0
期刊最新文献
Modelling of dishing for metal chemical mechanical polishing An orthogonal 6F/sup 2/ trench-sidewall vertical device cell for 4 Gb/16 Gb DRAM Highly reliable gate oxide under Fowler-Nordheim electron injection by deuterium pyrogenic oxidation and deuterated poly-Si deposition Liner-supported cylinder (LSC) technology to realize Ru/Ta/sub 2/O/sub 5//Ru capacitor for future DRAMs 30 nm physical gate length CMOS transistors with 1.0 ps n-MOS and 1.7 ps p-MOS gate delays
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
×
提示
您的信息不完整,为了账户安全,请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
现在去查看 取消
×
提示
确定
0
微信
客服QQ
Book学术公众号 扫码关注我们
反馈
×
意见反馈
请填写您的意见或建议
请填写您的手机或邮箱
已复制链接
已复制链接
快去分享给好友吧!
我知道了
×
扫码分享
扫码分享
Book学术官方微信
Book学术文献互助
Book学术文献互助群
群 号:481959085
Book学术
文献互助 智能选刊 最新文献 互助须知 联系我们:info@booksci.cn
Book学术提供免费学术资源搜索服务,方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。
Copyright © 2023 Book学术 All rights reserved.
ghs 京公网安备 11010802042870号 京ICP备2023020795号-1