{"title":"功率集成电路中模拟和混合信号电路的分析方法和策略","authors":"Gan Chye Siong Kenny, H. Beermann, S. Merzsch","doi":"10.1109/IPFA.2018.8452180","DOIUrl":null,"url":null,"abstract":"This paper describes the strategy and methods deployed to overcome complexities at various analysis steps systematically in analyzing analog or mix-signal circuits within power ICs. Methods and strategies include: 1.) Building up of universal application board as plug and play setup to verify the failure mode hence reducing setup time. 2.) Global plasma etching with end point detector to expose metal stacks which was implemented instead of FIB pad preparation prior to internal node measurement. 3.) Device characterization of suspicious transistors was measured on IC circuit while the IC is running in application mode. This method does not require physical circuit isolation. 4.) CAD simulation utilized as a tool for fault injection to confirm possible failure location. 5.) FIB as a local de-passivation technique to expose failing site or to perform further necessary fault isolation without altering the electrical failure.","PeriodicalId":382811,"journal":{"name":"2018 IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA)","volume":"7 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2018-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"Analysis Methods and Strategies of Analog and Mix Signal Circuits in Power IC\",\"authors\":\"Gan Chye Siong Kenny, H. Beermann, S. Merzsch\",\"doi\":\"10.1109/IPFA.2018.8452180\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper describes the strategy and methods deployed to overcome complexities at various analysis steps systematically in analyzing analog or mix-signal circuits within power ICs. Methods and strategies include: 1.) Building up of universal application board as plug and play setup to verify the failure mode hence reducing setup time. 2.) Global plasma etching with end point detector to expose metal stacks which was implemented instead of FIB pad preparation prior to internal node measurement. 3.) Device characterization of suspicious transistors was measured on IC circuit while the IC is running in application mode. This method does not require physical circuit isolation. 4.) CAD simulation utilized as a tool for fault injection to confirm possible failure location. 5.) FIB as a local de-passivation technique to expose failing site or to perform further necessary fault isolation without altering the electrical failure.\",\"PeriodicalId\":382811,\"journal\":{\"name\":\"2018 IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA)\",\"volume\":\"7 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2018-07-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2018 IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/IPFA.2018.8452180\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2018 IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/IPFA.2018.8452180","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Analysis Methods and Strategies of Analog and Mix Signal Circuits in Power IC
This paper describes the strategy and methods deployed to overcome complexities at various analysis steps systematically in analyzing analog or mix-signal circuits within power ICs. Methods and strategies include: 1.) Building up of universal application board as plug and play setup to verify the failure mode hence reducing setup time. 2.) Global plasma etching with end point detector to expose metal stacks which was implemented instead of FIB pad preparation prior to internal node measurement. 3.) Device characterization of suspicious transistors was measured on IC circuit while the IC is running in application mode. This method does not require physical circuit isolation. 4.) CAD simulation utilized as a tool for fault injection to confirm possible failure location. 5.) FIB as a local de-passivation technique to expose failing site or to perform further necessary fault isolation without altering the electrical failure.