M. Shikata, A. Nishino, R. Shigemasa, H. Fujishiro, S. Nishi, T. Ushikubo
{"title":"用于10gb /s光通信系统的相位检测器判决电路","authors":"M. Shikata, A. Nishino, R. Shigemasa, H. Fujishiro, S. Nishi, T. Ushikubo","doi":"10.1109/GAAS.1994.636969","DOIUrl":null,"url":null,"abstract":"A decision circuit with a function of detecting the phase difference between the input data signal and the clock signal is presented. The novel circuit technology has been used for the phase detectors. A linear and wide-rage phase detection was achieved as well as a wide phase margin of 288/spl deg/ and a small decision ambiguity of 27 mVPP up to 10 Gb/s.","PeriodicalId":328819,"journal":{"name":"Proceedings of 1994 IEEE GaAs IC Symposium","volume":"4 2","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1994-10-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":"{\"title\":\"A decision circuit with phase detectors for 10 Gb/s optical communication systems\",\"authors\":\"M. Shikata, A. Nishino, R. Shigemasa, H. Fujishiro, S. Nishi, T. Ushikubo\",\"doi\":\"10.1109/GAAS.1994.636969\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A decision circuit with a function of detecting the phase difference between the input data signal and the clock signal is presented. The novel circuit technology has been used for the phase detectors. A linear and wide-rage phase detection was achieved as well as a wide phase margin of 288/spl deg/ and a small decision ambiguity of 27 mVPP up to 10 Gb/s.\",\"PeriodicalId\":328819,\"journal\":{\"name\":\"Proceedings of 1994 IEEE GaAs IC Symposium\",\"volume\":\"4 2\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1994-10-16\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"1\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings of 1994 IEEE GaAs IC Symposium\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/GAAS.1994.636969\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings of 1994 IEEE GaAs IC Symposium","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/GAAS.1994.636969","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A decision circuit with phase detectors for 10 Gb/s optical communication systems
A decision circuit with a function of detecting the phase difference between the input data signal and the clock signal is presented. The novel circuit technology has been used for the phase detectors. A linear and wide-rage phase detection was achieved as well as a wide phase margin of 288/spl deg/ and a small decision ambiguity of 27 mVPP up to 10 Gb/s.