{"title":"基于单电子隧穿的二进制倍增","authors":"C. Lageweg, S. Cotofana, S. Vassiliadis","doi":"10.1109/ASAP.2004.10019","DOIUrl":null,"url":null,"abstract":"This work investigates single electron tunneling based implementations of 16 and 32-bit tree multipliers operating according to the single electron encoded logic paradigm. First, we propose implementations for a set of basic components (13/2 counter, 7/3 counter) and verify them by means of simulation. Second, we propose 16 and 32-bit tree multipliers based on these components, and analyze these multipliers in terms of area, delay and power consumption. Third, we investigate alternative designs for the 32-bit multiplier and conclude that the 7/3 counter based implementations are less effective than expected. We consequently propose improved 7/3 counters and evaluate the implications of these new designs on the area, delay and power consumption of the 16 and 32-bit multipliers.","PeriodicalId":120245,"journal":{"name":"Proceedings. 15th IEEE International Conference on Application-Specific Systems, Architectures and Processors, 2004.","volume":null,"pages":null},"PeriodicalIF":0.0000,"publicationDate":"2004-09-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"7","resultStr":"{\"title\":\"Binary multiplication based on single electron tunneling\",\"authors\":\"C. Lageweg, S. Cotofana, S. Vassiliadis\",\"doi\":\"10.1109/ASAP.2004.10019\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This work investigates single electron tunneling based implementations of 16 and 32-bit tree multipliers operating according to the single electron encoded logic paradigm. First, we propose implementations for a set of basic components (13/2 counter, 7/3 counter) and verify them by means of simulation. Second, we propose 16 and 32-bit tree multipliers based on these components, and analyze these multipliers in terms of area, delay and power consumption. Third, we investigate alternative designs for the 32-bit multiplier and conclude that the 7/3 counter based implementations are less effective than expected. We consequently propose improved 7/3 counters and evaluate the implications of these new designs on the area, delay and power consumption of the 16 and 32-bit multipliers.\",\"PeriodicalId\":120245,\"journal\":{\"name\":\"Proceedings. 15th IEEE International Conference on Application-Specific Systems, Architectures and Processors, 2004.\",\"volume\":null,\"pages\":null},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2004-09-27\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"7\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings. 15th IEEE International Conference on Application-Specific Systems, Architectures and Processors, 2004.\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ASAP.2004.10019\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings. 15th IEEE International Conference on Application-Specific Systems, Architectures and Processors, 2004.","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ASAP.2004.10019","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Binary multiplication based on single electron tunneling
This work investigates single electron tunneling based implementations of 16 and 32-bit tree multipliers operating according to the single electron encoded logic paradigm. First, we propose implementations for a set of basic components (13/2 counter, 7/3 counter) and verify them by means of simulation. Second, we propose 16 and 32-bit tree multipliers based on these components, and analyze these multipliers in terms of area, delay and power consumption. Third, we investigate alternative designs for the 32-bit multiplier and conclude that the 7/3 counter based implementations are less effective than expected. We consequently propose improved 7/3 counters and evaluate the implications of these new designs on the area, delay and power consumption of the 16 and 32-bit multipliers.