优化Au和In微碰撞三维芯片堆叠

W. Zhang, A. Matin, E. Beyne, W. Ruythooren
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引用次数: 11

摘要

3D芯片堆叠技术需要重复堆叠额外的层,而不会重新熔化堆栈较低水平的凸起。这可以通过瞬态液相(TLP)键合来实现,在此过程中,所有焊料都转化为具有比焊料本身更高熔点的金属间化合物。本文研究了Au/In在不同温度下的反应,以开发一种可靠的低温Au/In TLP键合工艺。结果表明,金属间化合物的形成动力学受扩散控制,Au/In反应的活化能与温度有关:在150℃以上和150℃以下,Au/In反应的活化能分别为0.46和0.23 eV。此外,在Au和In之间的薄Ti层在低温下是有效的扩散屏障,而在倒装晶片键合过程中,它不会抑制高温下金属间连接的形成。这使我们能够在TLP键合过程的不同阶段控制金属间化合物的形成。此外,为了实现TLP键合,最小厚度要求为0.5 mm。最后,在180℃的温度下成功制备了phi40至phi60 mum的Au/In TLP接头,并且焊料体积非常小(1 mum厚)。我们的phi40-60菊花接头的抗剪强度在6-20 MPa范围内,对于含有1380个直径为60妈妈的凸起的菊花链,电气连接率为100%。
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Optimizing Au and In micro-bumping for 3D chip stacking
3D chip stacking technology requires repeated stacking of additional layers without remelting the bumps at lower levels of the stack. This can be achieved by transient liquid phase (TLP) bonding during which all solder is transformed into intermetallic compounds that have higher melting points than the solder itself. In this paper, we study Au/In reaction at different temperatures in order to develop a robust low temperature Au/In TLP bonding process. It is shown that the kinetics of intermetallic compound formation is diffusion-controlled, and the activation energy of Au/In reaction is temperature-dependent: 0.46 and 0.23 eV for temperatures above and below 150degC, respectively. Moreover, a thin Ti layer between Au and In is found to be an effective diffusion barrier at low temperature, while it does not inhibit intermetallic joint formation at elevated temperatures during flip-chip bonding. This allows us to control the intermetallic formation during the distinct stages of TLP bonding process. In addition, a minimal In thickness of 0.5 mum is required in order to enable TLP bonding. Finally, Au/In TLP joints of phi40 to phi60 mum are successfully fabricated at 180degC and with very small solder volume (1 mum thick). The shear strength of our phi40-60 mum joints is in the range of 6-20 MPa, and the electrical connection yield is 100% for the daisy chain containing 1380 bumps with a diameter of 60 mum.
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