薄SOI上高压功率集成电路的前景

A. Nakagawa, N. Yasuhara, I. Omura, Y. Yamaguchi, T. Ogura, T. Matsudai
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引用次数: 39

摘要

绝缘体上硅技术在高压功率集成电路中应用前景广阔。如果施加电压的很大一部分由底部绝缘体层维持,则可以减少所需的SOI层厚度。SOI与沟槽或LOCOS的组合具有简化器件隔离和器件封装密度高的优点。薄SOI层由于载流子的存储量较少,将实现高压器件的高速开关。讨论了衬底偏压对器件特性和SOI技术电位的影响。
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Prospects of high voltage power ICs on thin SOI
Silicon on Insulator technology is promising for high voltage power IC applications. The required SOI layer thickness can be reduced if a large portion of the applied voltage is sustained by the bottom insulator layer. Combination of SOI and trenches or LOCOS has merits of simplified device isolation and high device packing density. Thin SOI layer will realize high-speed switching in high voltage devices because of the smaller amount of stored carriers. Substrate bias influences on device characteristics and potentials of SOI technology are discussed.<>
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