应用负群延迟有源电路使rc -线模型的传播延迟降低50%

B. Ravelo, A. Pérennec, M. Roy
{"title":"应用负群延迟有源电路使rc -线模型的传播延迟降低50%","authors":"B. Ravelo, A. Pérennec, M. Roy","doi":"10.1109/SPI.2008.4558347","DOIUrl":null,"url":null,"abstract":"This paper presents a new method developed to reduce the propagation delay by using a negative group delay (NGD) active circuit. Analytical expressions are proposed to demonstrate the validity of our approach in the case of an RC-transmission line model. The synthesis method of NGD circuits versus the line length is detailed. For a 0.5 Gbit/s digital signal and a 2-cm-long RC-line model, time-domain simulations carried out with a high-frequency circuit simulator showed that the 50% propagation delay was reduced by 94%. Finally, potential applications of this method to compensate for time delays in different interconnect configurations (VLSI, package, on-chip, long-line, ...) are discussed.","PeriodicalId":142239,"journal":{"name":"2008 12th IEEE Workshop on Signal Propagation on Interconnects","volume":"35 2","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2008-05-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"16","resultStr":"{\"title\":\"Application of negative group delay active circuits to reduce the 50% propagation Delay of RC-line model\",\"authors\":\"B. Ravelo, A. Pérennec, M. Roy\",\"doi\":\"10.1109/SPI.2008.4558347\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper presents a new method developed to reduce the propagation delay by using a negative group delay (NGD) active circuit. Analytical expressions are proposed to demonstrate the validity of our approach in the case of an RC-transmission line model. The synthesis method of NGD circuits versus the line length is detailed. For a 0.5 Gbit/s digital signal and a 2-cm-long RC-line model, time-domain simulations carried out with a high-frequency circuit simulator showed that the 50% propagation delay was reduced by 94%. Finally, potential applications of this method to compensate for time delays in different interconnect configurations (VLSI, package, on-chip, long-line, ...) are discussed.\",\"PeriodicalId\":142239,\"journal\":{\"name\":\"2008 12th IEEE Workshop on Signal Propagation on Interconnects\",\"volume\":\"35 2\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2008-05-12\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"16\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2008 12th IEEE Workshop on Signal Propagation on Interconnects\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/SPI.2008.4558347\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2008 12th IEEE Workshop on Signal Propagation on Interconnects","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/SPI.2008.4558347","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 16

摘要

本文提出了一种利用负群延迟(NGD)有源电路降低传输延迟的新方法。我们提出了解析表达式来证明我们的方法在rc传输线模型中的有效性。详细介绍了随线路长度变化的NGD电路的合成方法。对于0.5 Gbit/s的数字信号和2 cm长的rc线模型,用高频电路模拟器进行时域仿真表明,50%的传播延迟降低了94%。最后,讨论了该方法在不同互连结构(VLSI、封装、片上、长线等)中补偿时间延迟的潜在应用。
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Application of negative group delay active circuits to reduce the 50% propagation Delay of RC-line model
This paper presents a new method developed to reduce the propagation delay by using a negative group delay (NGD) active circuit. Analytical expressions are proposed to demonstrate the validity of our approach in the case of an RC-transmission line model. The synthesis method of NGD circuits versus the line length is detailed. For a 0.5 Gbit/s digital signal and a 2-cm-long RC-line model, time-domain simulations carried out with a high-frequency circuit simulator showed that the 50% propagation delay was reduced by 94%. Finally, potential applications of this method to compensate for time delays in different interconnect configurations (VLSI, package, on-chip, long-line, ...) are discussed.
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