Dong Chen, Zhao Xing, Zhilin Chen, Chenxi Zhao, Huihua Liu, K. Kang
{"title":"具有134%相对带宽的封装级驱动放大器","authors":"Dong Chen, Zhao Xing, Zhilin Chen, Chenxi Zhao, Huihua Liu, K. Kang","doi":"10.1109/EDAPS.2017.8276978","DOIUrl":null,"url":null,"abstract":"A CMOS package-level driver amplifier is presented. Since the inductor-less inter-stage matching network is utilized to enhance the bandwidth, the driver amplifier works from 0.72 ∼ 3.65 GHz with 134% relative bandwidth. Bonding wires for package are modeled using coupled lumped components and designed as parts of matching networks to enhance the power gain. The measured power gain is 27 dB with output referred P1dB is 8 dBm. The chip is fabricated in 65 nm CMOS technology, and ESD protection circuit is integrated. The size of the chip is 0.63 × 0.68 mm2.","PeriodicalId":329279,"journal":{"name":"2017 IEEE Electrical Design of Advanced Packaging and Systems Symposium (EDAPS)","volume":"43 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2017-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":"{\"title\":\"A package-level driver amplifier with 134% relative bandwidth\",\"authors\":\"Dong Chen, Zhao Xing, Zhilin Chen, Chenxi Zhao, Huihua Liu, K. Kang\",\"doi\":\"10.1109/EDAPS.2017.8276978\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A CMOS package-level driver amplifier is presented. Since the inductor-less inter-stage matching network is utilized to enhance the bandwidth, the driver amplifier works from 0.72 ∼ 3.65 GHz with 134% relative bandwidth. Bonding wires for package are modeled using coupled lumped components and designed as parts of matching networks to enhance the power gain. The measured power gain is 27 dB with output referred P1dB is 8 dBm. The chip is fabricated in 65 nm CMOS technology, and ESD protection circuit is integrated. The size of the chip is 0.63 × 0.68 mm2.\",\"PeriodicalId\":329279,\"journal\":{\"name\":\"2017 IEEE Electrical Design of Advanced Packaging and Systems Symposium (EDAPS)\",\"volume\":\"43 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2017-12-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"1\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2017 IEEE Electrical Design of Advanced Packaging and Systems Symposium (EDAPS)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/EDAPS.2017.8276978\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2017 IEEE Electrical Design of Advanced Packaging and Systems Symposium (EDAPS)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/EDAPS.2017.8276978","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A package-level driver amplifier with 134% relative bandwidth
A CMOS package-level driver amplifier is presented. Since the inductor-less inter-stage matching network is utilized to enhance the bandwidth, the driver amplifier works from 0.72 ∼ 3.65 GHz with 134% relative bandwidth. Bonding wires for package are modeled using coupled lumped components and designed as parts of matching networks to enhance the power gain. The measured power gain is 27 dB with output referred P1dB is 8 dBm. The chip is fabricated in 65 nm CMOS technology, and ESD protection circuit is integrated. The size of the chip is 0.63 × 0.68 mm2.
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