一种新的防静电功率放大器设计方法

2007 7th International Conference on ASIC Pub Date : 2007-10-01 DOI:10.1109/ICASIC.2007.4415890

X. Guan, Guang Chen, Lin Lin, Xin Wang, Albert Wang, Lee Yang, B. Zhao

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引用次数: 1

摘要

本文提出了一种新的ESD感知功率放大器(PA)设计方法，采用s参数建模和输出阻抗再匹配技术，实现ESD+PA全芯片设计优化。采用0.18 μ m RFCMOS技术设计和实现的5kv防静电2.4 GHz PA电路验证了新方法。实验表明，由于静电放电的影响，聚光镜的性能有很大的下降，而采用新的防静电设计方法可以恢复这种下降。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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A new ESD-aware power amplifier design method

This paper presents a new ESD-aware power amplifier (PA) design method, featuring S-parameter modeling and output impedance re-matching techniques, to achieve ESD+PA full-chip design optimization. The new method is verified using a 5 kV ESD-protected 2.4 GHz PA circuit designed and implemented in a 0.18 mum RFCMOS technology. Experiment shows substantial performance degradation of PA due to ESD effect, which can be recovered by using the new ESD-aware ESD design method.

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2007 7th International Conference on ASIC

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