{"title":"利用高级综合技术进行空间协处理器设计探索","authors":"Avinash Lakshminarayana, Sumit Ahuja, S. Shukla","doi":"10.1109/ISQED.2010.5450474","DOIUrl":null,"url":null,"abstract":"Hardware/software co-design has been an area of research for a few decades. Currently co-design is utilized to create hardware coprocessors for compute intensive tasks of a system (which otherwise, performed in software, will not meet the performance goals). Design of correct hardware coprocessors with area, timing and power constraints is a time consuming task. In this paper, we present a methodology to alleviate this problem up to a certain extent. First, we show how to adopt a high-level synthesis tool in design space exploration to converge towards efficient hardware coprocessors. Second, we show, through a series of case studies that, a system-level approach, keeping platform specific optimizations in mind, can help in doing such an exploration efficiently.","PeriodicalId":369046,"journal":{"name":"2010 11th International Symposium on Quality Electronic Design (ISQED)","volume":"21 4","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2010-03-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"5","resultStr":"{\"title\":\"Coprocessor design space exploration using high level synthesis\",\"authors\":\"Avinash Lakshminarayana, Sumit Ahuja, S. Shukla\",\"doi\":\"10.1109/ISQED.2010.5450474\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Hardware/software co-design has been an area of research for a few decades. Currently co-design is utilized to create hardware coprocessors for compute intensive tasks of a system (which otherwise, performed in software, will not meet the performance goals). Design of correct hardware coprocessors with area, timing and power constraints is a time consuming task. In this paper, we present a methodology to alleviate this problem up to a certain extent. First, we show how to adopt a high-level synthesis tool in design space exploration to converge towards efficient hardware coprocessors. Second, we show, through a series of case studies that, a system-level approach, keeping platform specific optimizations in mind, can help in doing such an exploration efficiently.\",\"PeriodicalId\":369046,\"journal\":{\"name\":\"2010 11th International Symposium on Quality Electronic Design (ISQED)\",\"volume\":\"21 4\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2010-03-22\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"5\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2010 11th International Symposium on Quality Electronic Design (ISQED)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ISQED.2010.5450474\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2010 11th International Symposium on Quality Electronic Design (ISQED)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISQED.2010.5450474","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Coprocessor design space exploration using high level synthesis
Hardware/software co-design has been an area of research for a few decades. Currently co-design is utilized to create hardware coprocessors for compute intensive tasks of a system (which otherwise, performed in software, will not meet the performance goals). Design of correct hardware coprocessors with area, timing and power constraints is a time consuming task. In this paper, we present a methodology to alleviate this problem up to a certain extent. First, we show how to adopt a high-level synthesis tool in design space exploration to converge towards efficient hardware coprocessors. Second, we show, through a series of case studies that, a system-level approach, keeping platform specific optimizations in mind, can help in doing such an exploration efficiently.