嵌入式系统专用非易失性主存储器

Kwangyoon Lee, A. Orailoglu
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引用次数: 26

摘要

内存子系统一直被认为是嵌入式系统中最关键的组件之一,而且随着应用需求的多样化,其复杂性也在不断增加。现代嵌入式系统通常配备多个异构存储设备,以满足不同的需求和约束。NAND闪存因其在成本、功耗、容量和非易失性等方面的突出优势而被广泛应用于数据存储。然而,在NAND闪存中,读写访问的内在成本在性能和访问粒度上是极不相称的。随之而来的数据管理复杂性和性能下降阻碍了NAND闪存的采用。在本文中,我们介绍了一种高效的非易失性主存储器架构,该架构结合了应用特定信息来开发基于NAND闪存的主存储器。该架构提供了一个统一的非易失性主存储器解决方案,减轻了由于存储子系统日益复杂而导致的设计复杂性。我们的架构通过利用高效的地址空间管理和基于准确应用程序行为分析的动态数据迁移,积极地将基于NAND的系统的开销和冗余降到最低。我们还提出了一种基于运行时工作负载分析的高并行内存架构,通过在多个闪存上进行主动和动态的数据重新分配。实验结果表明,我们提出的架构显着提高了与标准DRAM访问周期相当的平均存储器访问周期时间,并且通过自主损耗均衡和最小化程序/擦除操作大大延长了器件的生命周期。
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Application specific non-volatile primary memory for embedded systems
Memory subsystems have been considered as one of the most critical components in embedded systems and furthermore, displaying increasing complexity as application requirements diversify. Modern embedded systems are generally equipped with multiple heterogeneous memory devices to satisfy diverse requirements and constraints. NAND flash memory has been widely adopted for data storage because of its outstanding benefits on cost, power, capacity and non-volatility. However, in NAND flash memory, the intrinsic costs for the read and write accesses are highly disproportionate in performance and access granularity. The consequent data management complexity and performance deterioration have precluded the adoption of NAND flash memory. In this paper, we introduce a highly effective non-volatile primary memory architecture which incorporates application specific information to develop a NAND flash based primary memory. The proposed architecture provides a unified non-volatile primary memory solution which relieves design complications caused by the growing complexity in memory subsystems. Our architecture aggressively minimizes the overhead and redundancy of the NAND based systems by exploiting efficient address space management and dynamic data migration based on accurate application behavioral analysis. We also propose a highly parallelized memory architecture through an active and dynamic data redistribution over the multiple flash memories based on run-time workload analysis. The experimental results show that our proposed architecture significantly enhances average memory access cycle time which is comparable to the standard DRAM access cycle time and also considerably prolongs the device life-cycle by autonomous wear-leveling and minimizing the program/erase operations.
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