一种改进的近似平方函数的电路设计

2005 6th International Conference on ASIC Pub Date : 2005-10-24 DOI:10.1109/ICASIC.2005.1611512

Zhang Xun, Jin Weiwei, Jin Dong-ming

{"title":"一种改进的近似平方函数的电路设计","authors":"Zhang Xun, Jin Weiwei, Jin Dong-ming","doi":"10.1109/ICASIC.2005.1611512","DOIUrl":null,"url":null,"abstract":"An improved approach to design the approximate squaring function is presented in this paper. It is implemented through a simple combinational logic circuit with fewer transistors. In addition, the maximum relative error (MRE) and average relative error (ARE) of squaring approximation are both improved compared with the previous methods. The algorithm is implemented by a VLSI design of 7-bit approximate squaring function.","PeriodicalId":431034,"journal":{"name":"2005 6th International Conference on ASIC","volume":null,"pages":null},"PeriodicalIF":0.0000,"publicationDate":"2005-10-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"4","resultStr":"{\"title\":\"Circuit design of an improved approximate squaring function\",\"authors\":\"Zhang Xun, Jin Weiwei, Jin Dong-ming\",\"doi\":\"10.1109/ICASIC.2005.1611512\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"An improved approach to design the approximate squaring function is presented in this paper. It is implemented through a simple combinational logic circuit with fewer transistors. In addition, the maximum relative error (MRE) and average relative error (ARE) of squaring approximation are both improved compared with the previous methods. The algorithm is implemented by a VLSI design of 7-bit approximate squaring function.\",\"PeriodicalId\":431034,\"journal\":{\"name\":\"2005 6th International Conference on ASIC\",\"volume\":null,\"pages\":null},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2005-10-24\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"4\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2005 6th International Conference on ASIC\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ICASIC.2005.1611512\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2005 6th International Conference on ASIC","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICASIC.2005.1611512","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}

引用次数: 4

摘要

本文提出了一种改进的近似平方函数设计方法。它是通过一个简单的组合逻辑电路和更少的晶体管实现的。此外，平方近似的最大相对误差(MRE)和平均相对误差(ARE)都比以前的方法有所提高。该算法通过7位近似平方函数的VLSI设计实现。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

查看原文

微信好友朋友圈 QQ好友复制链接

本刊更多论文

Circuit design of an improved approximate squaring function

An improved approach to design the approximate squaring function is presented in this paper. It is implemented through a simple combinational logic circuit with fewer transistors. In addition, the maximum relative error (MRE) and average relative error (ARE) of squaring approximation are both improved compared with the previous methods. The algorithm is implemented by a VLSI design of 7-bit approximate squaring function.

求助全文

通过发布文献求助，成功后即可免费获取论文全文。去求助

来源期刊

2005 6th International Conference on ASIC

自引率

0.00%

发文量

期刊最新文献

A CMOS continuous-time Gm-C filter and programmable gain amplifier for WPAN receivers A VLSI architecture for motion compensation interpolation in H.264/AVC Transition traversal coverage estimation for symbolic model checking Power reduction in high-speed inter-chip data communications An optimization of VLSI architecture for DFE used in Ethernet