High-performance implementation of SM2 based on FPGA

This brief presents an FPGA-based ultra-high performance ECC implementation over SM2 prime field which can resist SPA. This processor is designed with bottom-up optimization focused on SM2 and make the best of advantages of modern FPGA. To counteract SPA more efficiently and reduce time cost, traditional MPL algorithm is modified to be the main algorithm which can execute point addition (PA) and point double (PD) in parallel. Then PA and PD are designed to be full-isochronous modules invoked by main algorithm to maximize the efficiency. Finite field operations adopt DSP blocks to increase frequency. Spliced multipliers are matched with same-frequency adders in the introduced pipeline structure, which improve hardware utilization to more than 95 percent. Run on Altera StratixII EP2S30F672 FPGA, this SM2 processor whose frequency reaches 62.3 MHz can be performed at a rate of about 1.3k point multiplications per second, and it only costs 8 DSPs and 4742 ALMs. Compared with other related works, our architecture offers not only ultra-high performance but also deep research about the FPGA-based implementation of SM2.