分布式RC线路的时延分析

V. Rao
{"title":"分布式RC线路的时延分析","authors":"V. Rao","doi":"10.1145/217474.217557","DOIUrl":null,"url":null,"abstract":"This paper reviews the step-response of the semi-infinite distributed RC line and focuses mainly on the step-response of a finite-length RC line with a capacitive load termination, which is the most common model for a wire inside the present day integrated CMOS chips. In particular, we obtain the values of some of the common threshold-crossing times at the output of such a line and show that even the simplest first order lumped II-approximation to the finite-length RC line terminated with a capacitive load is good enough for obtaining the 50% and 63.2% threshold-crossing times of the step-response. Higher order lumped approximations are necessary for more accurate predictions of the 10% and 90% threshold-crossing times.","PeriodicalId":422297,"journal":{"name":"32nd Design Automation Conference","volume":"43 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"29","resultStr":"{\"title\":\"Delay Analysis of the Distributed RC Line\",\"authors\":\"V. Rao\",\"doi\":\"10.1145/217474.217557\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper reviews the step-response of the semi-infinite distributed RC line and focuses mainly on the step-response of a finite-length RC line with a capacitive load termination, which is the most common model for a wire inside the present day integrated CMOS chips. In particular, we obtain the values of some of the common threshold-crossing times at the output of such a line and show that even the simplest first order lumped II-approximation to the finite-length RC line terminated with a capacitive load is good enough for obtaining the 50% and 63.2% threshold-crossing times of the step-response. Higher order lumped approximations are necessary for more accurate predictions of the 10% and 90% threshold-crossing times.\",\"PeriodicalId\":422297,\"journal\":{\"name\":\"32nd Design Automation Conference\",\"volume\":\"43 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1900-01-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"29\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"32nd Design Automation Conference\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1145/217474.217557\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"32nd Design Automation Conference","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1145/217474.217557","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 29

摘要

本文综述了半无限分布RC线的阶跃响应,重点研究了带容性负载端接的有限长度RC线的阶跃响应,这是目前集成CMOS芯片中最常见的导线模型。特别是,我们得到了这样一条线的输出端的一些常见阈值跨越时间的值,并表明,即使是对以电容负载结尾的有限长度RC线的最简单的一阶集总ii近似,也足以获得阶跃响应的50%和63.2%的阈值跨越时间。为了更准确地预测10%和90%的阈值交叉时间,需要更高阶的集总近似。
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Delay Analysis of the Distributed RC Line
This paper reviews the step-response of the semi-infinite distributed RC line and focuses mainly on the step-response of a finite-length RC line with a capacitive load termination, which is the most common model for a wire inside the present day integrated CMOS chips. In particular, we obtain the values of some of the common threshold-crossing times at the output of such a line and show that even the simplest first order lumped II-approximation to the finite-length RC line terminated with a capacitive load is good enough for obtaining the 50% and 63.2% threshold-crossing times of the step-response. Higher order lumped approximations are necessary for more accurate predictions of the 10% and 90% threshold-crossing times.
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