容错WSI阵列处理器:伯杰码在并行算术逻辑单元中的使用

1990 Proceedings. International Conference on Wafer Scale Integration Pub Date : 1990-01-23 DOI:10.1109/ICWSI.1990.63902

V. Piuri

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摘要

讨论了容错WSI阵列处理器的设计:使用伯杰码来引入算术和逻辑运算的统一方法。在基于并行计算单元的体系结构中，对单向错误的检测和编码技术的成本进行了评估。提出了不同的结构用于并发错误检测和故障定位。

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Fault-tolerant WSI array processors: the use of Berger codes in parallel arithmetic-logic units

Design of fault-tolerant WSI array processors is discussed: the use of Berger codes is presented to introduce a unifying approach both for arithmetic and logic operations. Detection of unidirectional errors and costs of the coding technique are evaluated in architectures based upon parallel computing units. Different structures are proposed for concurrent error detection and fault-localisation.<>

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1990 Proceedings. International Conference on Wafer Scale Integration

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