一种0.35 /spl mu/m沟槽栅极MOSFET，在感应开关过程中具有超低状态电阻和高抗破坏能力

12th International Symposium on Power Semiconductor Devices & ICs. Proceedings (Cat. No.00CH37094) Pub Date : 2000-05-22 DOI:10.1109/ISPSD.2000.856847

A. Narazaki, J. Maruyama, T. Kayumi, H. Hamachi, J. Moritani, S. Hine

{"title":"一种0.35 /spl mu/m沟槽栅极MOSFET，在感应开关过程中具有超低状态电阻和高抗破坏能力","authors":"A. Narazaki, J. Maruyama, T. Kayumi, H. Hamachi, J. Moritani, S. Hine","doi":"10.1109/ISPSD.2000.856847","DOIUrl":null,"url":null,"abstract":"This paper describes performance of 20 V class N-channel MOSFET using 0.35 /spl mu/m trench gate structure. It has two characteristics mainly. The first is an ultra low on state resistance by shrinking the trench gate width and increasing cell densities. The other is a high destruction immunity during the inductive switching by optimizing a trench depth. The measured specific on-resistance (Ron,sp) is 25% reduction comparing conventional one. Furthermore, this device can provide high avalanche current density during the inductive switching of JD=30 A/mm/sup 2/.","PeriodicalId":260241,"journal":{"name":"12th International Symposium on Power Semiconductor Devices & ICs. Proceedings (Cat. No.00CH37094)","volume":"29 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2000-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"21","resultStr":"{\"title\":\"A 0.35 /spl mu/m trench gate MOSFET with an ultra low on state resistance and a high destruction immunity during the inductive switching\",\"authors\":\"A. Narazaki, J. Maruyama, T. Kayumi, H. Hamachi, J. Moritani, S. Hine\",\"doi\":\"10.1109/ISPSD.2000.856847\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper describes performance of 20 V class N-channel MOSFET using 0.35 /spl mu/m trench gate structure. It has two characteristics mainly. The first is an ultra low on state resistance by shrinking the trench gate width and increasing cell densities. The other is a high destruction immunity during the inductive switching by optimizing a trench depth. The measured specific on-resistance (Ron,sp) is 25% reduction comparing conventional one. Furthermore, this device can provide high avalanche current density during the inductive switching of JD=30 A/mm/sup 2/.\",\"PeriodicalId\":260241,\"journal\":{\"name\":\"12th International Symposium on Power Semiconductor Devices & ICs. Proceedings (Cat. No.00CH37094)\",\"volume\":\"29 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2000-05-22\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"21\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"12th International Symposium on Power Semiconductor Devices & ICs. Proceedings (Cat. No.00CH37094)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ISPSD.2000.856847\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"12th International Symposium on Power Semiconductor Devices & ICs. Proceedings (Cat. No.00CH37094)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISPSD.2000.856847","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}

引用次数: 21

摘要

本文介绍了采用0.35 /spl mu/m沟槽栅结构的20v级n沟道MOSFET的性能。它主要有两个特点。首先是通过缩小沟槽栅极宽度和增加电池密度来实现超低的通态电阻。二是通过优化沟槽深度来提高电感开关的抗破坏能力。测量的比导通电阻(Ron,sp)比传统的降低了25%。此外，该器件在JD=30 A/mm/sup /的感应开关过程中可提供高雪崩电流密度。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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A 0.35 /spl mu/m trench gate MOSFET with an ultra low on state resistance and a high destruction immunity during the inductive switching

This paper describes performance of 20 V class N-channel MOSFET using 0.35 /spl mu/m trench gate structure. It has two characteristics mainly. The first is an ultra low on state resistance by shrinking the trench gate width and increasing cell densities. The other is a high destruction immunity during the inductive switching by optimizing a trench depth. The measured specific on-resistance (Ron,sp) is 25% reduction comparing conventional one. Furthermore, this device can provide high avalanche current density during the inductive switching of JD=30 A/mm/sup 2/.

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12th International Symposium on Power Semiconductor Devices & ICs. Proceedings (Cat. No.00CH37094)

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