Parallel Convolutional Neural Network (CNN) Accelerators Based on Stochastic Computing

Stochastic computing (SC), which processes the data in the form of random bit streams, has been used in neural networks due to simple logic gates performing complex arithmetic and the inherent high error-tolerance. However, SC-based neural network accelerators suffer from high latency, random fluctuations, and large hardware cost of pseudo-random number generators (PRNG), thus diminishing the advantages of stochastic computing. In this paper, we address these problems with a novel technique of generating bit streams in parallel, which needs only one clock for conversion and significantly reduces the hardware cost. Based on this parallel bitstream generator, we further present two kinds of convolutional neural network (CNN) accelerator architectures with digital and analog circuits, respectively, showing great potential for low-power applications.