利用位混合全加法器设计进位前瞻加法器以提高性能

Meghana Rao Ravula, Abhishek Potharaju, R. Vidyadhar
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引用次数: 3

摘要

数字电路又称逻辑电路,逻辑电路主要进行加、减、除、乘等运算。在这里,加法器是在当今数字时代有多种方式的电路,我们设计的主要目标是通过一个位混合全加法器电路的先决条件,并将其与许多加法器设计风格进行比较,如使用10个晶体管设计的全加法器,使用13个晶体管的全加法器,使用28个晶体管的全加法器,一点涟漪——加法器使用混合加法器,在细节做比较研究,全面一点混合加法器是由于其能耗少,延迟和功率延迟产品这些参数研究了它们作为性能指标,并设计携带向前看加法器使用一个混合全加器,携带向前看是它知道是加法器电路,升级最快的速度通过减少时间确定带位。校准每个数字的位置,或者它将传播并产生进位。Carry Look Ahead采用Cadence virtuoso 90nm技术设计和实现,电源电压为1.0v。
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Designing Carry Look Ahead Adder to Enrich Performance using One Bit Hybrid Full Adder
Digital circuits also known for logic circuits ,logic circuits mainly operate on addition, subtraction, division multiplication etc.. here ,Adders are the circuits which has copious ways of smearing for todays digital era, the main grail of our design is to extrapolate and whip up low power Carry look ahead adder by taking prerequisite of one bit hybrid Full Adder circuit and comparing it with numerous adders design styles like a Full Adder designed using 10 transistors, full adder using 13 Transistors, full adder using 28 Transistors, Ripple -Carry Adder using one bit hybrid adder ,looking within of details make comparative study where in, one bit hybrid full adder is considered because of its Less Power consumption ,delay and power delay product these parameters were studied them as performance metrics, and designed Carry Look Ahead adder using one bit hybrid full adder, as Carry Look Ahead is considered it is knows as fastest adder circuits which upgrades the speed by reducing the time by determining the carry bits. calibrates each and every digit’s position either it will be propagating and generate a carry bit. Carry Look Ahead is designed and implemented in Cadence virtuoso 90nm technology with 1.0v of supply voltage.
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