D. Becher, G. Banerjee, R. Basco, C. Hung, K. Kuhn, W. Shih
{"title":"90纳米CMOS技术的噪声性能","authors":"D. Becher, G. Banerjee, R. Basco, C. Hung, K. Kuhn, W. Shih","doi":"10.1109/MWSYM.2004.1335785","DOIUrl":null,"url":null,"abstract":"This work describes the noise figure performance of CMOS transistors at the 90 nm technology node. Noise parameters are measured from 2-18 GHz, resulting in a minimum noise figure less than 2 dB across the range of measured frequencies for both NMOS and PMOS. Data is presented showing the effect of total gate width, gate length, and bias on the noise parameters.","PeriodicalId":334675,"journal":{"name":"2004 IEEE MTT-S International Microwave Symposium Digest (IEEE Cat. No.04CH37535)","volume":"164 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2004-06-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"8","resultStr":"{\"title\":\"Noise performance of 90 nm CMOS technology\",\"authors\":\"D. Becher, G. Banerjee, R. Basco, C. Hung, K. Kuhn, W. Shih\",\"doi\":\"10.1109/MWSYM.2004.1335785\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This work describes the noise figure performance of CMOS transistors at the 90 nm technology node. Noise parameters are measured from 2-18 GHz, resulting in a minimum noise figure less than 2 dB across the range of measured frequencies for both NMOS and PMOS. Data is presented showing the effect of total gate width, gate length, and bias on the noise parameters.\",\"PeriodicalId\":334675,\"journal\":{\"name\":\"2004 IEEE MTT-S International Microwave Symposium Digest (IEEE Cat. No.04CH37535)\",\"volume\":\"164 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2004-06-06\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"8\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2004 IEEE MTT-S International Microwave Symposium Digest (IEEE Cat. No.04CH37535)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/MWSYM.2004.1335785\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2004 IEEE MTT-S International Microwave Symposium Digest (IEEE Cat. No.04CH37535)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/MWSYM.2004.1335785","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
This work describes the noise figure performance of CMOS transistors at the 90 nm technology node. Noise parameters are measured from 2-18 GHz, resulting in a minimum noise figure less than 2 dB across the range of measured frequencies for both NMOS and PMOS. Data is presented showing the effect of total gate width, gate length, and bias on the noise parameters.
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