{"title":"高级加密标准的VHDL实现","authors":"H. Loban","doi":"10.35598/mcfpga.2019.014","DOIUrl":null,"url":null,"abstract":"A new original approach to realization of AES algorithm on FPGA is proposed. Problems of VHDL modeling of AES ciphering and deciphering are considered. Keywords—AES, triple DES, encryption, decryption, FPGA, VHDL","PeriodicalId":439446,"journal":{"name":"I International Scientific and Practical Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":"{\"title\":\"A VHDL Implemetation of the Advanced Encryption Standard\",\"authors\":\"H. Loban\",\"doi\":\"10.35598/mcfpga.2019.014\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A new original approach to realization of AES algorithm on FPGA is proposed. Problems of VHDL modeling of AES ciphering and deciphering are considered. Keywords—AES, triple DES, encryption, decryption, FPGA, VHDL\",\"PeriodicalId\":439446,\"journal\":{\"name\":\"I International Scientific and Practical Conference\",\"volume\":\"1 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1900-01-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"2\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"I International Scientific and Practical Conference\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.35598/mcfpga.2019.014\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"I International Scientific and Practical Conference","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.35598/mcfpga.2019.014","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A VHDL Implemetation of the Advanced Encryption Standard
A new original approach to realization of AES algorithm on FPGA is proposed. Problems of VHDL modeling of AES ciphering and deciphering are considered. Keywords—AES, triple DES, encryption, decryption, FPGA, VHDL
京公网安备 11010802042870号
京ICP备2023020795号-1
分享
求助内容：
应助结果提醒方式：
扫码关注我们
