Pub Date : 1900-01-01DOI: 10.35598/mcfpga.2019.014
H. Loban
A new original approach to realization of AES algorithm on FPGA is proposed. Problems of VHDL modeling of AES ciphering and deciphering are considered. Keywords—AES, triple DES, encryption, decryption, FPGA, VHDL
{"title":"A VHDL Implemetation of the Advanced Encryption Standard","authors":"H. Loban","doi":"10.35598/mcfpga.2019.014","DOIUrl":"https://doi.org/10.35598/mcfpga.2019.014","url":null,"abstract":"A new original approach to realization of AES algorithm on FPGA is proposed. Problems of VHDL modeling of AES ciphering and deciphering are considered. Keywords—AES, triple DES, encryption, decryption, FPGA, VHDL","PeriodicalId":439446,"journal":{"name":"I International Scientific and Practical Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121132601","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.35598/MCFPGA.2019.001
Oleg Avrunin, T. Nosova, Valerii V. Semenets
—A laboratory workshop was developed, consisting of a series of works aimed at studying and studying the principles of microcontroller programming, practical implementation of interaction with sensors, organization of work with input / output devices, and development of interface devices. By changing sensors that are connected to laboratory mockups or real equipment, and reprogramming the microcontroller system, you can perform laboratory work on almost all engineering profile courses.
{"title":"Experience of Developing a Laboratory Base for the Study of Modern Microprocessor Systems","authors":"Oleg Avrunin, T. Nosova, Valerii V. Semenets","doi":"10.35598/MCFPGA.2019.001","DOIUrl":"https://doi.org/10.35598/MCFPGA.2019.001","url":null,"abstract":"—A laboratory workshop was developed, consisting of a series of works aimed at studying and studying the principles of microcontroller programming, practical implementation of interaction with sensors, organization of work with input / output devices, and development of interface devices. By changing sensors that are connected to laboratory mockups or real equipment, and reprogramming the microcontroller system, you can perform laboratory work on almost all engineering profile courses.","PeriodicalId":439446,"journal":{"name":"I International Scientific and Practical Conference","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133365348","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.35598/MCFPGA.2019.010
I. Svyd, O. Maltsev, O. Zubkov, L. Saikivska
Matlab is a high-level language and an interactive environment that can help to analyze data, develop algorithms, create models and applications. There are many extensions for Matlab. One of these extensions is the Xilinx System Generator for DSP, a key component of the Xilinx specialized digital signal processing platform, that allows to implement DSP algorithms with less time costs than traditional RTL design. Keywords—MATLAB, VHDL, XILINX, VIVADO.
Matlab是一种高级语言和交互式环境，可以帮助分析数据，开发算法，创建模型和应用程序。Matlab有许多扩展。其中一个扩展是用于DSP的Xilinx System Generator，这是Xilinx专用数字信号处理平台的关键组件，它允许以比传统RTL设计更少的时间成本实现DSP算法。关键词:matlab, VHDL, XILINX, VIVADO。
{"title":"Matlab Use in Design of Digital Systems on the FPGA in CAD Xilinx VIVADO","authors":"I. Svyd, O. Maltsev, O. Zubkov, L. Saikivska","doi":"10.35598/MCFPGA.2019.010","DOIUrl":"https://doi.org/10.35598/MCFPGA.2019.010","url":null,"abstract":"Matlab is a high-level language and an interactive environment that can help to analyze data, develop algorithms, create models and applications. There are many extensions for Matlab. One of these extensions is the Xilinx System Generator for DSP, a key component of the Xilinx specialized digital signal processing platform, that allows to implement DSP algorithms with less time costs than traditional RTL design. Keywords—MATLAB, VHDL, XILINX, VIVADO.","PeriodicalId":439446,"journal":{"name":"I International Scientific and Practical Conference","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117185227","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.35598/mcfpga.2019.015
Oleksandr Vorgul
Approaches to half band filter realization are considered. Ways of implementation are discussed. Possibilities for obtaining FIR or IIR realizations are mentioned. Keywords—FPGA, half band filter, digital signal processing, analytical signal
{"title":"Approaches Half Band Filter Realization for Means FPGA","authors":"Oleksandr Vorgul","doi":"10.35598/mcfpga.2019.015","DOIUrl":"https://doi.org/10.35598/mcfpga.2019.015","url":null,"abstract":"Approaches to half band filter realization are considered. Ways of implementation are discussed. Possibilities for obtaining FIR or IIR realizations are mentioned. Keywords—FPGA, half band filter, digital signal processing, analytical signal","PeriodicalId":439446,"journal":{"name":"I International Scientific and Practical Conference","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127716798","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.35598/MCFPGA.2019.008
I. Svyd, O. Maltsev, L. Saikivska, O. Zubkov
The work of the Xilinx FPGA of the 7th series was reviewed, as well as a comparative description of its families. Keywords—FPGA, DSP, XADC, Xilinx, Spartan-7, Artix-7, Kintex-7, Virtex-7.
{"title":"Review of Seventh Series FPGA Xilinx","authors":"I. Svyd, O. Maltsev, L. Saikivska, O. Zubkov","doi":"10.35598/MCFPGA.2019.008","DOIUrl":"https://doi.org/10.35598/MCFPGA.2019.008","url":null,"abstract":"The work of the Xilinx FPGA of the 7th series was reviewed, as well as a comparative description of its families. Keywords—FPGA, DSP, XADC, Xilinx, Spartan-7, Artix-7, Kintex-7, Virtex-7.","PeriodicalId":439446,"journal":{"name":"I International Scientific and Practical Conference","volume":"44 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134319720","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.35598/MCFPGA.2019.006
Oleksandr Vorgul
This article is devoted to design of a measurement system based on specialized FPGA. A balance of ACD and DAC channels through output from one side and computation power of FPGA from another side is considered. Possibilities for obtaining one more tool for screening the signal processing is proposed Keywords—FPGA, analog signal, digital signal processing, measurement system
{"title":"How to Use Equipment to Measure the Analog Signal by Means of FPGA System","authors":"Oleksandr Vorgul","doi":"10.35598/MCFPGA.2019.006","DOIUrl":"https://doi.org/10.35598/MCFPGA.2019.006","url":null,"abstract":"This article is devoted to design of a measurement system based on specialized FPGA. A balance of ACD and DAC channels through output from one side and computation power of FPGA from another side is considered. Possibilities for obtaining one more tool for screening the signal processing is proposed Keywords—FPGA, analog signal, digital signal processing, measurement system","PeriodicalId":439446,"journal":{"name":"I International Scientific and Practical Conference","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126784144","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.35598/MCFPGA.2019.005
Andrij Verygha
A way of organizing parallel processes without the use of real-time operating systems is described, which is convenient for writing programs for microcontrollers with a small size of program memory. Keywords—microcontroller, program, parallel process
{"title":"Organization Features of Parallel Processes in Programs for Microcontrollers with a Small Amount of Program Memory","authors":"Andrij Verygha","doi":"10.35598/MCFPGA.2019.005","DOIUrl":"https://doi.org/10.35598/MCFPGA.2019.005","url":null,"abstract":"A way of organizing parallel processes without the use of real-time operating systems is described, which is convenient for writing programs for microcontrollers with a small size of program memory. Keywords—microcontroller, program, parallel process","PeriodicalId":439446,"journal":{"name":"I International Scientific and Practical Conference","volume":"32 12","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120865087","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.35598/MCFPGA.2019.011
V. Moroz
—FPGA systems development has long ceased to be limited to simply writing code in hardware description languages (HDL); and as the number of logical resources and the complexity of projects increase, approaches to designing systems on FPGAs have been repeatedly revised. One of the turns of development was the introduction of soft processors into projects — essentially ordinary microprocessors but assembled on FPGA resources. Unfortunately, despite the relative difficulty of developing software-processor systems, many trying to “raise” this topic face difficulties in mastering, because they do not know where to find the necessary information.
{"title":"Application of Xilinx Series 7 on FPGA (XADC)","authors":"V. Moroz","doi":"10.35598/MCFPGA.2019.011","DOIUrl":"https://doi.org/10.35598/MCFPGA.2019.011","url":null,"abstract":"—FPGA systems development has long ceased to be limited to simply writing code in hardware description languages (HDL); and as the number of logical resources and the complexity of projects increase, approaches to designing systems on FPGAs have been repeatedly revised. One of the turns of development was the introduction of soft processors into projects — essentially ordinary microprocessors but assembled on FPGA resources. Unfortunately, despite the relative difficulty of developing software-processor systems, many trying to “raise” this topic face difficulties in mastering, because they do not know where to find the necessary information.","PeriodicalId":439446,"journal":{"name":"I International Scientific and Practical Conference","volume":"68 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114689062","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.35598/mcfpga.2019.003
O. Zubkov, I. Svyd, O. Maltsev, L. Saikivska
Considered the implementation of in-circuit analysis of logical signals in digital devices synthesized in Xilinx Field-Programmable Gate Array. Designed a digital control device streaming analog-to-digital converter. An analysis of the results of the analog-digital conversion was carried out and measures were taken to smooth out the false results of the conversion. Keywords—analog-digital converter, Field-Programmable Gate Array, in-circuit debugging, Logic Analyzer, bus, clock signal .
{"title":"In-circuit Signal Analysis in the Development of Digital Devices in Vivado 2018","authors":"O. Zubkov, I. Svyd, O. Maltsev, L. Saikivska","doi":"10.35598/mcfpga.2019.003","DOIUrl":"https://doi.org/10.35598/mcfpga.2019.003","url":null,"abstract":"Considered the implementation of in-circuit analysis of logical signals in digital devices synthesized in Xilinx Field-Programmable Gate Array. Designed a digital control device streaming analog-to-digital converter. An analysis of the results of the analog-digital conversion was carried out and measures were taken to smooth out the false results of the conversion. Keywords—analog-digital converter, Field-Programmable Gate Array, in-circuit debugging, Logic Analyzer, bus, clock signal .","PeriodicalId":439446,"journal":{"name":"I International Scientific and Practical Conference","volume":"108 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122531433","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.35598/MCFPGA.2019.002
M. Miroshnyk, Pavlo Galkin, O. Zaichenko, R. Tsekhmistro
Testability increasing methods by introducing hardware redundancy into the circuit implementation are sufficiently developed and widely used in the design. Since the construction of the testing sequence is based on the use of automaton diagrams, it eliminates the need to analyze the circuit implementation of the remote control when building a diagnostic experiment. This approach allows us to extend the class of detectable faults, which in structural-analytical test generation methods is limited, as a rule, to a multitude of single constant faults. The use of automaton models in the construction of tests allows to detect any malfunction that changes the automaton diagram of a serviceable remote control and does not increase the number of states of remote control memory elements. There was described finite state machine using hardware description language. The method of computer-aided design of the easytested control FSM by introducing the hardware redundancy is presented in the paper. The FSM model is represented in VHDL in the form of the FSM template. The solution way is to add additional fragments of the VHDL code, which ensure the forced setting of the FSM into an arbitrary state without the use of synchronizing sequences. The use of the shift register in the memory part of the control FSM for organizing the path scanning was considered. The method of FSM state table expansion, which ensures the mode of bypassing all nodes of the FSM’ state diagram in the diagnostic mode was proposed. Keywords—easy tested finite state machine, Hamiltonian cycle, distinguishing sequence, homing sequence, shift register.
{"title":"Testability Increasing Method by Introducing Hardware Redundancy in the Easy-tested Finite State Machines","authors":"M. Miroshnyk, Pavlo Galkin, O. Zaichenko, R. Tsekhmistro","doi":"10.35598/MCFPGA.2019.002","DOIUrl":"https://doi.org/10.35598/MCFPGA.2019.002","url":null,"abstract":"Testability increasing methods by introducing hardware redundancy into the circuit implementation are sufficiently developed and widely used in the design. Since the construction of the testing sequence is based on the use of automaton diagrams, it eliminates the need to analyze the circuit implementation of the remote control when building a diagnostic experiment. This approach allows us to extend the class of detectable faults, which in structural-analytical test generation methods is limited, as a rule, to a multitude of single constant faults. The use of automaton models in the construction of tests allows to detect any malfunction that changes the automaton diagram of a serviceable remote control and does not increase the number of states of remote control memory elements. There was described finite state machine using hardware description language. The method of computer-aided design of the easytested control FSM by introducing the hardware redundancy is presented in the paper. The FSM model is represented in VHDL in the form of the FSM template. The solution way is to add additional fragments of the VHDL code, which ensure the forced setting of the FSM into an arbitrary state without the use of synchronizing sequences. The use of the shift register in the memory part of the control FSM for organizing the path scanning was considered. The method of FSM state table expansion, which ensures the mode of bypassing all nodes of the FSM’ state diagram in the diagnostic mode was proposed. Keywords—easy tested finite state machine, Hamiltonian cycle, distinguishing sequence, homing sequence, shift register.","PeriodicalId":439446,"journal":{"name":"I International Scientific and Practical Conference","volume":"76 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131361868","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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