A Josephson ternary memory circuit

A novel ternary logic memory circuit using Josephson junctions is described. The principle of the ternary memory circuit proposed here is based on the persistent circulating current in the superconducting loop in the clockwise and the counter clockwise directions. As the gate for writing and reading operation of the memory, the three-junction SQUID and the JCTL which is constructed by combination of two two-junction SQUIDs are used. In order to develop the memory circuit, we have made the simulations to determine the most suitable circuit parameters to the memory cell and then fabricated the circuit based on 2 /spl mu/m minimum line width technology. The simulation results show satisfactory operations of the memory circuit, which agree well with the experiment results. The advantages of the proposed memory circuit are capability of high speed computation, low power consumption and very simple construction with less number of elements due to the ternary operation.