J. Maneatis, Jaeha Kim, Iain McClatchie, J. Maxey, Manjusha Shankaradas
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引用次数: 103
摘要
自偏锁相环采用采样前馈滤波器网络和多级反线性可编程电流镜实现恒定环路动态，该动态随参考频率缩放，不受倍增因子、输出频率和pvt的影响。该锁相环的倍增范围为1至4096，输出抖动小于1.7%。采用0.13/spl μ m CMOS制造，面积0.182mm/sup 2/，电源为1.5V。
A self-biased PLL uses a sample feed-forward filter network and a multistage inverse-linear programmable current mirror for constant loop dynamics that scale with reference frequency and are independent of multiplication factor, output frequency, and PVT. The PLL achieves a multiplication range of 1 to 4096 with less than 1.7% output jitter. Fabricated in 0.13/spl mu/m CMOS, the area is 0.182mm/sup 2/ and the supply is 1.5V.
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