{"title":"一种新型高性能低功耗低时钟振荡TSPC触发器","authors":"Yingbo Hu, Zhaolin Li, R. Zhou","doi":"10.1109/ICASIC.2007.4415584","DOIUrl":null,"url":null,"abstract":"A new type of pulse-triggered true single phase clock (TSPC) flip-flop with low threshold voltage clock transistor and its several improved structures are proposed for high-performance low-power applications. Due to low clock-swing and double-edge triggering, the power consumption of the clock network is estimated to reduce by 78%. HSPICE simulation with 0.18 mum CMOS technology shows that their delay, power dissipation and PDP are reduced by 20~44%, 40~56% and 61~72% respectively, when compared with the existing Low-Swing Clock Double-Edge Triggered Flip-Flop (LSDFF).","PeriodicalId":120984,"journal":{"name":"2007 7th International Conference on ASIC","volume":"326 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2007-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"6","resultStr":"{\"title\":\"a new type of high-performance low-power low clock-swing TSPC flip-flop\",\"authors\":\"Yingbo Hu, Zhaolin Li, R. Zhou\",\"doi\":\"10.1109/ICASIC.2007.4415584\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A new type of pulse-triggered true single phase clock (TSPC) flip-flop with low threshold voltage clock transistor and its several improved structures are proposed for high-performance low-power applications. Due to low clock-swing and double-edge triggering, the power consumption of the clock network is estimated to reduce by 78%. HSPICE simulation with 0.18 mum CMOS technology shows that their delay, power dissipation and PDP are reduced by 20~44%, 40~56% and 61~72% respectively, when compared with the existing Low-Swing Clock Double-Edge Triggered Flip-Flop (LSDFF).\",\"PeriodicalId\":120984,\"journal\":{\"name\":\"2007 7th International Conference on ASIC\",\"volume\":\"326 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2007-10-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"6\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2007 7th International Conference on ASIC\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ICASIC.2007.4415584\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2007 7th International Conference on ASIC","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICASIC.2007.4415584","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 6
摘要
提出了一种新型的低阈值电压时钟晶体管脉冲触发真单相时钟触发器及其几种改进结构,用于高性能低功耗应用。由于低时钟摆幅和双边触发,时钟网络的功耗估计降低了78%。采用0.18 mm CMOS技术的HSPICE仿真结果表明,与现有的低摆幅时钟双边触发触发器(LSDFF)相比,它们的延迟、功耗和PDP分别降低了20~44%、40~56%和61~72%。
a new type of high-performance low-power low clock-swing TSPC flip-flop
A new type of pulse-triggered true single phase clock (TSPC) flip-flop with low threshold voltage clock transistor and its several improved structures are proposed for high-performance low-power applications. Due to low clock-swing and double-edge triggering, the power consumption of the clock network is estimated to reduce by 78%. HSPICE simulation with 0.18 mum CMOS technology shows that their delay, power dissipation and PDP are reduced by 20~44%, 40~56% and 61~72% respectively, when compared with the existing Low-Swing Clock Double-Edge Triggered Flip-Flop (LSDFF).