{"title":"基于Xilinx Virtex fpga的TMR系统自参考洗涤器","authors":"I. Herrera-Alzu, M. López-Vallejo","doi":"10.1007/978-3-642-24154-3_14","DOIUrl":null,"url":null,"abstract":"","PeriodicalId":428747,"journal":{"name":"International Workshop on Power and Timing Modeling, Optimization and Simulation","volume":"169 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2011-09-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"9","resultStr":"{\"title\":\"Self-reference Scrubber for TMR Systems Based on Xilinx Virtex FPGAs\",\"authors\":\"I. Herrera-Alzu, M. López-Vallejo\",\"doi\":\"10.1007/978-3-642-24154-3_14\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"\",\"PeriodicalId\":428747,\"journal\":{\"name\":\"International Workshop on Power and Timing Modeling, Optimization and Simulation\",\"volume\":\"169 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2011-09-26\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"9\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"International Workshop on Power and Timing Modeling, Optimization and Simulation\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1007/978-3-642-24154-3_14\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"International Workshop on Power and Timing Modeling, Optimization and Simulation","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1007/978-3-642-24154-3_14","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}