{"title":"基于机器学习的知识产权保护水印解码技术","authors":"Mr. R. Senthil Ganesh","doi":"10.17762/ijnpme.v8i03.77","DOIUrl":null,"url":null,"abstract":"The Watermarking is an Intellectual Property (IP) Protection method. It can ensure Field-Programmable Gate Array (FPGA) IPs from encroachment. The IP security of equipment and programming structures is the most significant prerequisite for some FPGA licensed innovation merchants. Advanced watermarking has become a creative innovation for IP assurance as of late. This paper proposes the Publicly Verifiable Watermarking plan for licensed innovation insurance in FPGA structure. The Zero-Knowledge Verification Protocol and Data Matrix strategy are utilized in this watermarking location method. The time stepping is likewise utilized with the zero-information check convention and it can versatility oppose the delicate data spillage and implanting assaults, and is along these lines hearty to the cheating from the prover, verifier, or outsider. The encryption keys are additionally utilized with the information lattice technique and it can restrict the watermark, and make the watermark vigorous against assaults. In this proposed zero-information technique zero rate asset, timing and watermarking overhead can be accomplished. The proposed zero-information watermarking plan causes zero overhead. In this proposed information lattice technique signal-rich-workmanship code picture, can be portrayed. The proposed information network watermarking plan encodes the copyright confirmation data. The zero-information confirmation convention and information grid technique proposed in this paper is executed by MATLAB R2014a in which C programming language is utilized in it and ModelSim 10.5b in which VHDL coding is utilized in it, are running on a PC. The combination instrument Xilinx ISE 14.5 is likewise used to confirm and actualize the watermarking plan.","PeriodicalId":297822,"journal":{"name":"International Journal of New Practices in Management and Engineering","volume":"185 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"11","resultStr":"{\"title\":\"Watermark Decoding Technique using Machine Learning for Intellectual Property Protection\",\"authors\":\"Mr. R. Senthil Ganesh\",\"doi\":\"10.17762/ijnpme.v8i03.77\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"The Watermarking is an Intellectual Property (IP) Protection method. It can ensure Field-Programmable Gate Array (FPGA) IPs from encroachment. The IP security of equipment and programming structures is the most significant prerequisite for some FPGA licensed innovation merchants. Advanced watermarking has become a creative innovation for IP assurance as of late. This paper proposes the Publicly Verifiable Watermarking plan for licensed innovation insurance in FPGA structure. The Zero-Knowledge Verification Protocol and Data Matrix strategy are utilized in this watermarking location method. The time stepping is likewise utilized with the zero-information check convention and it can versatility oppose the delicate data spillage and implanting assaults, and is along these lines hearty to the cheating from the prover, verifier, or outsider. The encryption keys are additionally utilized with the information lattice technique and it can restrict the watermark, and make the watermark vigorous against assaults. In this proposed zero-information technique zero rate asset, timing and watermarking overhead can be accomplished. The proposed zero-information watermarking plan causes zero overhead. In this proposed information lattice technique signal-rich-workmanship code picture, can be portrayed. The proposed information network watermarking plan encodes the copyright confirmation data. The zero-information confirmation convention and information grid technique proposed in this paper is executed by MATLAB R2014a in which C programming language is utilized in it and ModelSim 10.5b in which VHDL coding is utilized in it, are running on a PC. The combination instrument Xilinx ISE 14.5 is likewise used to confirm and actualize the watermarking plan.\",\"PeriodicalId\":297822,\"journal\":{\"name\":\"International Journal of New Practices in Management and Engineering\",\"volume\":\"185 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1900-01-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"11\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"International Journal of New Practices in Management and Engineering\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.17762/ijnpme.v8i03.77\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"International Journal of New Practices in Management and Engineering","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.17762/ijnpme.v8i03.77","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 11
摘要
水印是一种知识产权保护方法。它可以确保现场可编程门阵列(FPGA) ip不受侵犯。设备和编程结构的IP安全性是一些FPGA授权创新商家最重要的先决条件。先进的水印技术已成为近年来知识产权保障的一项创造性创新。提出了FPGA结构下许可创新保险的公开可验证水印方案。该水印定位方法采用了零知识验证协议和数据矩阵策略。时间步进同样与零信息检查约定一起使用,它可以多用途地防止微妙的数据泄漏和植入攻击,并且沿着这些路线可以防止来自证明者,验证者或局外人的作弊。在密钥的基础上结合信息格技术对水印进行约束,使水印具有较强的抗攻击能力。在这种零信息技术中,可以实现零速率资产、定时和水印开销。提出的零信息水印方案的开销为零。在这种提出的信息点阵技术中,信号丰富的工艺码图,可以被描绘出来。提出的信息网络水印方案对版权确认数据进行编码。本文提出的零信息确认约定和信息网格技术是在PC机上运行的,使用的是MATLAB R2014a,其中使用的是C编程语言,ModelSim 10.5b使用的是VHDL编码。同样使用Xilinx ISE 14.5组合仪器来确认和实现水印计划。
Watermark Decoding Technique using Machine Learning for Intellectual Property Protection
The Watermarking is an Intellectual Property (IP) Protection method. It can ensure Field-Programmable Gate Array (FPGA) IPs from encroachment. The IP security of equipment and programming structures is the most significant prerequisite for some FPGA licensed innovation merchants. Advanced watermarking has become a creative innovation for IP assurance as of late. This paper proposes the Publicly Verifiable Watermarking plan for licensed innovation insurance in FPGA structure. The Zero-Knowledge Verification Protocol and Data Matrix strategy are utilized in this watermarking location method. The time stepping is likewise utilized with the zero-information check convention and it can versatility oppose the delicate data spillage and implanting assaults, and is along these lines hearty to the cheating from the prover, verifier, or outsider. The encryption keys are additionally utilized with the information lattice technique and it can restrict the watermark, and make the watermark vigorous against assaults. In this proposed zero-information technique zero rate asset, timing and watermarking overhead can be accomplished. The proposed zero-information watermarking plan causes zero overhead. In this proposed information lattice technique signal-rich-workmanship code picture, can be portrayed. The proposed information network watermarking plan encodes the copyright confirmation data. The zero-information confirmation convention and information grid technique proposed in this paper is executed by MATLAB R2014a in which C programming language is utilized in it and ModelSim 10.5b in which VHDL coding is utilized in it, are running on a PC. The combination instrument Xilinx ISE 14.5 is likewise used to confirm and actualize the watermarking plan.