{"title":"技术对低压CMOS和BiCMOS开关延迟的影响","authors":"K.L. Davis, J. Yuan","doi":"10.1109/SECON.1998.673319","DOIUrl":null,"url":null,"abstract":"An alternative switching delay reduction technique for CMOS and BiCMOS digital circuits is examined. A simplified BSIM3V2 model equation is used to analyze CMOS inverter delay for different V/sub DD/, T/sub ox/, and V/sub T/. PSPICE BiCMOS delay results are presented over a wide range of V/sub DD/, T/sub ox/, and V/sub T/.","PeriodicalId":281991,"journal":{"name":"Proceedings IEEE Southeastcon '98 'Engineering for a New Era'","volume":"17 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1998-04-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"Impact of technology on low-voltage CMOS and BiCMOS switching delay\",\"authors\":\"K.L. Davis, J. Yuan\",\"doi\":\"10.1109/SECON.1998.673319\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"An alternative switching delay reduction technique for CMOS and BiCMOS digital circuits is examined. A simplified BSIM3V2 model equation is used to analyze CMOS inverter delay for different V/sub DD/, T/sub ox/, and V/sub T/. PSPICE BiCMOS delay results are presented over a wide range of V/sub DD/, T/sub ox/, and V/sub T/.\",\"PeriodicalId\":281991,\"journal\":{\"name\":\"Proceedings IEEE Southeastcon '98 'Engineering for a New Era'\",\"volume\":\"17 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1998-04-24\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings IEEE Southeastcon '98 'Engineering for a New Era'\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/SECON.1998.673319\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings IEEE Southeastcon '98 'Engineering for a New Era'","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/SECON.1998.673319","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Impact of technology on low-voltage CMOS and BiCMOS switching delay
An alternative switching delay reduction technique for CMOS and BiCMOS digital circuits is examined. A simplified BSIM3V2 model equation is used to analyze CMOS inverter delay for different V/sub DD/, T/sub ox/, and V/sub T/. PSPICE BiCMOS delay results are presented over a wide range of V/sub DD/, T/sub ox/, and V/sub T/.
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