{"title":"一种复杂、高可靠性电子系统的测试和诊断方法","authors":"S. Pateras, P. McHugh","doi":"10.1109/AUTEST.1997.633652","DOIUrl":null,"url":null,"abstract":"A test and diagnosis methodology that is based on built-in self-test(BIST) is defined and described. A BIST solution based on a maintainable system architecture is described that includes the technology, and tools needed for the development of chip, board, and system BIST. This architecture is based on the IEEE 1149.5 MTM-Bus at the backplane level and the IEEE 1149.1 (JTAG) Boundary Scan Architecture at the chip level.","PeriodicalId":369132,"journal":{"name":"1997 IEEE Autotestcon Proceedings AUTOTESTCON '97. IEEE Systems Readiness Technology Conference. Systems Readiness Supporting Global Needs and Awareness in the 21st Century","volume":"14 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1997-09-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"7","resultStr":"{\"title\":\"BIST: a test a diagnosis methodology for complex, high reliability electronics systems\",\"authors\":\"S. Pateras, P. McHugh\",\"doi\":\"10.1109/AUTEST.1997.633652\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A test and diagnosis methodology that is based on built-in self-test(BIST) is defined and described. A BIST solution based on a maintainable system architecture is described that includes the technology, and tools needed for the development of chip, board, and system BIST. This architecture is based on the IEEE 1149.5 MTM-Bus at the backplane level and the IEEE 1149.1 (JTAG) Boundary Scan Architecture at the chip level.\",\"PeriodicalId\":369132,\"journal\":{\"name\":\"1997 IEEE Autotestcon Proceedings AUTOTESTCON '97. IEEE Systems Readiness Technology Conference. Systems Readiness Supporting Global Needs and Awareness in the 21st Century\",\"volume\":\"14 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1997-09-22\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"7\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"1997 IEEE Autotestcon Proceedings AUTOTESTCON '97. IEEE Systems Readiness Technology Conference. Systems Readiness Supporting Global Needs and Awareness in the 21st Century\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/AUTEST.1997.633652\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"1997 IEEE Autotestcon Proceedings AUTOTESTCON '97. IEEE Systems Readiness Technology Conference. Systems Readiness Supporting Global Needs and Awareness in the 21st Century","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/AUTEST.1997.633652","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
BIST: a test a diagnosis methodology for complex, high reliability electronics systems
A test and diagnosis methodology that is based on built-in self-test(BIST) is defined and described. A BIST solution based on a maintainable system architecture is described that includes the technology, and tools needed for the development of chip, board, and system BIST. This architecture is based on the IEEE 1149.5 MTM-Bus at the backplane level and the IEEE 1149.1 (JTAG) Boundary Scan Architecture at the chip level.
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