1997 IEEE Autotestcon Proceedings AUTOTESTCON '97. IEEE Systems Readiness Technology Conference. Systems Readiness Supporting Global Needs and Awareness in the 21st Century最新文献
Pub Date : 1997-09-22DOI: 10.1109/AUTEST.1997.633608
M. Thrailkill, Lek Leekhool
This paper describes an implementation of a Test Foundation Framework (TFF) as described in the draft IEEE-Std-1226-1993, A Broad Based Environment for Test (ABBET). The ABBET Object Model schema described in IS010303-11, EXPRESS-G language diagrams is compared to a TFF implementation expressed as LabVIEW G diagrams.
{"title":"Implementing a Test Foundation Framework in LabVIEW","authors":"M. Thrailkill, Lek Leekhool","doi":"10.1109/AUTEST.1997.633608","DOIUrl":"https://doi.org/10.1109/AUTEST.1997.633608","url":null,"abstract":"This paper describes an implementation of a Test Foundation Framework (TFF) as described in the draft IEEE-Std-1226-1993, A Broad Based Environment for Test (ABBET). The ABBET Object Model schema described in IS010303-11, EXPRESS-G language diagrams is compared to a TFF implementation expressed as LabVIEW G diagrams.","PeriodicalId":369132,"journal":{"name":"1997 IEEE Autotestcon Proceedings AUTOTESTCON '97. IEEE Systems Readiness Technology Conference. Systems Readiness Supporting Global Needs and Awareness in the 21st Century","volume":"59 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-09-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127200319","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-09-22DOI: 10.1109/AUTEST.1997.633685
S.A. Macfarlane
One of the biggest test related topics of this decade has been the use of COTS hardware and software. This has been driven by the need to reduce development and maintenance costs, and to try and achieve a commonality between test systems. The systems integrator then has the task of taking many different industry and de-facto standards, and seamlessly building them into the final system. This paper deals with the development of a Common Underlying Architecture (CUA) which forms the "glue" to interface between many different standards such as ATLAS and VXIplug&play. This provides an open development and run-time system where the customer can choose from several different software languages and operating systems, whilst maintaining a common operator interface, a degree of resilience to obsolescence and the capability to extend the use of the Test System. The concept and definition of a CUA is currently the subject of on-going studies within the UK MoD. Various packaging and mounting options are discussed which allow the system to be configured for the particular application from factory test through to rugged field deployable systems.
{"title":"A common underlying architecture approach to test systems design","authors":"S.A. Macfarlane","doi":"10.1109/AUTEST.1997.633685","DOIUrl":"https://doi.org/10.1109/AUTEST.1997.633685","url":null,"abstract":"One of the biggest test related topics of this decade has been the use of COTS hardware and software. This has been driven by the need to reduce development and maintenance costs, and to try and achieve a commonality between test systems. The systems integrator then has the task of taking many different industry and de-facto standards, and seamlessly building them into the final system. This paper deals with the development of a Common Underlying Architecture (CUA) which forms the \"glue\" to interface between many different standards such as ATLAS and VXIplug&play. This provides an open development and run-time system where the customer can choose from several different software languages and operating systems, whilst maintaining a common operator interface, a degree of resilience to obsolescence and the capability to extend the use of the Test System. The concept and definition of a CUA is currently the subject of on-going studies within the UK MoD. Various packaging and mounting options are discussed which allow the system to be configured for the particular application from factory test through to rugged field deployable systems.","PeriodicalId":369132,"journal":{"name":"1997 IEEE Autotestcon Proceedings AUTOTESTCON '97. IEEE Systems Readiness Technology Conference. Systems Readiness Supporting Global Needs and Awareness in the 21st Century","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-09-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125102545","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-09-22DOI: 10.1109/AUTEST.1997.633580
L. Venetsky, S. Singer
This paper describes a system that automatically generates tests for an analog Unit Under Test (UUT) in learning mode, and then deploys the system for fault detection and isolation in the production mode. The NGTG consists of the following main components: a) minimized input test pattern generator, b) UUT simulator, and last but not least c) evaluation system. The NGTG is a process that utilizes Fuzzy Artmap neural network for fault diagnostics and detection and genetic algorithm for test generation and fault coverage optimization.
本文介绍了一个在学习模式下自动生成模拟被测单元(Unit Under Test, UUT)的测试，然后在生产模式下部署该系统进行故障检测和隔离的系统。NGTG由以下主要部分组成:a)最小化输入测试模式发生器，b) UUT模拟器，最后但并非最不重要的是c)评估系统。NGTG是一个利用模糊Artmap神经网络进行故障诊断和检测，利用遗传算法进行测试生成和故障覆盖优化的过程。
{"title":"Next generation test generator (NGTG) for analog circuits","authors":"L. Venetsky, S. Singer","doi":"10.1109/AUTEST.1997.633580","DOIUrl":"https://doi.org/10.1109/AUTEST.1997.633580","url":null,"abstract":"This paper describes a system that automatically generates tests for an analog Unit Under Test (UUT) in learning mode, and then deploys the system for fault detection and isolation in the production mode. The NGTG consists of the following main components: a) minimized input test pattern generator, b) UUT simulator, and last but not least c) evaluation system. The NGTG is a process that utilizes Fuzzy Artmap neural network for fault diagnostics and detection and genetic algorithm for test generation and fault coverage optimization.","PeriodicalId":369132,"journal":{"name":"1997 IEEE Autotestcon Proceedings AUTOTESTCON '97. IEEE Systems Readiness Technology Conference. Systems Readiness Supporting Global Needs and Awareness in the 21st Century","volume":"137 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-09-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122345634","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-09-22DOI: 10.1109/AUTEST.1997.633662
K. O'Toole
This paper discusses a graphical programming environment for ATLAS developed using Commercial Off The Shelf(COTS) software tools. This environment, known as Visual ATLAS, contains a revolutionary new approach to TPS development. The Visual ATLAS graphical programming environment provides an iconic representation of the ATLAS program now and structure. This includes test objects, variable declaration, loop/branch constructs procedures, module definition and more. Code reusability is supported via availability of an object library and software boilerplates. Because Visual ATLAS dramatically reduces the time required to develop ATLAS programs, users experience a substantial productivity gain. This results from ease of use, as well as simplified code maintenance and reuse. With Visual ATLAS, you build an ATLAS object framework instead of writing test programs. To specify program now, you build a now-chart like representation of the Test Program. This is an intuitive design environment for test technicians and engineers. This frees the programmer from working out the many syntactical details of conventional ATLAS programming. Objects are selected from a toolbox and are interconnected to other objects upon a sequence line to identify program now. This technique frees the programmer from the linear architecture of test-based ATLAS development.
{"title":"Graphical programming environment for ATLAS","authors":"K. O'Toole","doi":"10.1109/AUTEST.1997.633662","DOIUrl":"https://doi.org/10.1109/AUTEST.1997.633662","url":null,"abstract":"This paper discusses a graphical programming environment for ATLAS developed using Commercial Off The Shelf(COTS) software tools. This environment, known as Visual ATLAS, contains a revolutionary new approach to TPS development. The Visual ATLAS graphical programming environment provides an iconic representation of the ATLAS program now and structure. This includes test objects, variable declaration, loop/branch constructs procedures, module definition and more. Code reusability is supported via availability of an object library and software boilerplates. Because Visual ATLAS dramatically reduces the time required to develop ATLAS programs, users experience a substantial productivity gain. This results from ease of use, as well as simplified code maintenance and reuse. With Visual ATLAS, you build an ATLAS object framework instead of writing test programs. To specify program now, you build a now-chart like representation of the Test Program. This is an intuitive design environment for test technicians and engineers. This frees the programmer from working out the many syntactical details of conventional ATLAS programming. Objects are selected from a toolbox and are interconnected to other objects upon a sequence line to identify program now. This technique frees the programmer from the linear architecture of test-based ATLAS development.","PeriodicalId":369132,"journal":{"name":"1997 IEEE Autotestcon Proceedings AUTOTESTCON '97. IEEE Systems Readiness Technology Conference. Systems Readiness Supporting Global Needs and Awareness in the 21st Century","volume":"99 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-09-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114588115","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-09-22DOI: 10.1109/AUTEST.1997.633605
T. Jurcak
We are now reaping the benefits of an Object-Oriented software implementation of an ABBET (IEEE-1226) Signal-Oriented Test Framework. In our factory, we have created test software that is devoid of any knowledge of the instruments in our test set. Because of this, we can now choose whether we want a voltage measurement to be made by IEEE-488 Digital Multimeter (DMM) or VXI Oscilloscope instruments or even a hand-held DMM just prior to run-time. When an instrument fails or becomes obsolete, we can execute our test software on different testers or with different instrument types without impacting the test software. We can change the instruments in our Multiple Missile Factory standard test set without affecting the several configurations of test software that are controlled by separate organizations. One test suite, developed using the framework on a test set comprised of IEEE-488 instruments, was effortlessly moved to the VXI-based standard test set. In addition to the hardware independence, the framework supports a highly abstract test language that has allowed us to create generalized test methods that have greatly eased our effort to reuse test algorithms among our programs.
{"title":"An instrument-independent test software framework allows both hardware and software reuse","authors":"T. Jurcak","doi":"10.1109/AUTEST.1997.633605","DOIUrl":"https://doi.org/10.1109/AUTEST.1997.633605","url":null,"abstract":"We are now reaping the benefits of an Object-Oriented software implementation of an ABBET (IEEE-1226) Signal-Oriented Test Framework. In our factory, we have created test software that is devoid of any knowledge of the instruments in our test set. Because of this, we can now choose whether we want a voltage measurement to be made by IEEE-488 Digital Multimeter (DMM) or VXI Oscilloscope instruments or even a hand-held DMM just prior to run-time. When an instrument fails or becomes obsolete, we can execute our test software on different testers or with different instrument types without impacting the test software. We can change the instruments in our Multiple Missile Factory standard test set without affecting the several configurations of test software that are controlled by separate organizations. One test suite, developed using the framework on a test set comprised of IEEE-488 instruments, was effortlessly moved to the VXI-based standard test set. In addition to the hardware independence, the framework supports a highly abstract test language that has allowed us to create generalized test methods that have greatly eased our effort to reuse test algorithms among our programs.","PeriodicalId":369132,"journal":{"name":"1997 IEEE Autotestcon Proceedings AUTOTESTCON '97. IEEE Systems Readiness Technology Conference. Systems Readiness Supporting Global Needs and Awareness in the 21st Century","volume":"61 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-09-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129581873","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-09-22DOI: 10.1109/AUTEST.1997.633625
S. Freschi, T.A. Holland, W.A. Broadus
Operations and support (O&S) costs account for between 50 and 60% of the Navy's Total Obligation Authority (TOA). Affordable Readiness is the primary means by which the Navy will reduce these costs to create savings for investments in recapitalization and modernization of operational capability necessary to perform our mission. Affordable readiness is a business practice with four interrelated elements: flexible sustainment; sustained maintenance planning; total cost of ownership; and rightsourcing. Our challenge in the Automatic Test Systems (ATS) community is to engage in this process to provide a capability such that when avionics reliability requires it, intermediate level support is an effective and affordable support solution. We must, however, re-engineer our business processes to support affordable readiness in the Navy to ensure the products we provide meet our customers requirements. This paper will translate the business processes of acquiring and managing automatic test equipment (ATE) and test program sets (TPSs) into the four elements of affordable readiness and a cohesive vision of the future, while highlighting the opportunities end challenges confronting Government managers and our industry partners.
{"title":"Achieving affordable readiness in naval aviation maintenance through the acquisition and management of ATE and TPSs-opportunities and challenges","authors":"S. Freschi, T.A. Holland, W.A. Broadus","doi":"10.1109/AUTEST.1997.633625","DOIUrl":"https://doi.org/10.1109/AUTEST.1997.633625","url":null,"abstract":"Operations and support (O&S) costs account for between 50 and 60% of the Navy's Total Obligation Authority (TOA). Affordable Readiness is the primary means by which the Navy will reduce these costs to create savings for investments in recapitalization and modernization of operational capability necessary to perform our mission. Affordable readiness is a business practice with four interrelated elements: flexible sustainment; sustained maintenance planning; total cost of ownership; and rightsourcing. Our challenge in the Automatic Test Systems (ATS) community is to engage in this process to provide a capability such that when avionics reliability requires it, intermediate level support is an effective and affordable support solution. We must, however, re-engineer our business processes to support affordable readiness in the Navy to ensure the products we provide meet our customers requirements. This paper will translate the business processes of acquiring and managing automatic test equipment (ATE) and test program sets (TPSs) into the four elements of affordable readiness and a cohesive vision of the future, while highlighting the opportunities end challenges confronting Government managers and our industry partners.","PeriodicalId":369132,"journal":{"name":"1997 IEEE Autotestcon Proceedings AUTOTESTCON '97. IEEE Systems Readiness Technology Conference. Systems Readiness Supporting Global Needs and Awareness in the 21st Century","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-09-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128745158","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-09-22DOI: 10.1109/AUTEST.1997.633652
S. Pateras, P. McHugh
A test and diagnosis methodology that is based on built-in self-test(BIST) is defined and described. A BIST solution based on a maintainable system architecture is described that includes the technology, and tools needed for the development of chip, board, and system BIST. This architecture is based on the IEEE 1149.5 MTM-Bus at the backplane level and the IEEE 1149.1 (JTAG) Boundary Scan Architecture at the chip level.
{"title":"BIST: a test a diagnosis methodology for complex, high reliability electronics systems","authors":"S. Pateras, P. McHugh","doi":"10.1109/AUTEST.1997.633652","DOIUrl":"https://doi.org/10.1109/AUTEST.1997.633652","url":null,"abstract":"A test and diagnosis methodology that is based on built-in self-test(BIST) is defined and described. A BIST solution based on a maintainable system architecture is described that includes the technology, and tools needed for the development of chip, board, and system BIST. This architecture is based on the IEEE 1149.5 MTM-Bus at the backplane level and the IEEE 1149.1 (JTAG) Boundary Scan Architecture at the chip level.","PeriodicalId":369132,"journal":{"name":"1997 IEEE Autotestcon Proceedings AUTOTESTCON '97. IEEE Systems Readiness Technology Conference. Systems Readiness Supporting Global Needs and Awareness in the 21st Century","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-09-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121291523","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-09-22DOI: 10.1109/AUTEST.1997.633559
D. Rolince
Simulation model development and test program integration can account for over half the effort spent on digital TPS development. Digital test development in a Virtual Test environment can result in substantial TPS cost reductions through a combination of VHDL device model reuse and ATE environment simulation. Technology developed under the VTest contract sponsored by the U.S. Air Force Wright Laboratory Manufacturing Technology Directorate enables fault simulation of devices supported by VITAL libraries, thereby extending the use of VHDL into test program generation. Simulation driven VTest methodologies enable development of digital test programs completely off-line and with the ability to target virtually any digital ATE.
{"title":"Applying Virtual Test principles to digital test program development","authors":"D. Rolince","doi":"10.1109/AUTEST.1997.633559","DOIUrl":"https://doi.org/10.1109/AUTEST.1997.633559","url":null,"abstract":"Simulation model development and test program integration can account for over half the effort spent on digital TPS development. Digital test development in a Virtual Test environment can result in substantial TPS cost reductions through a combination of VHDL device model reuse and ATE environment simulation. Technology developed under the VTest contract sponsored by the U.S. Air Force Wright Laboratory Manufacturing Technology Directorate enables fault simulation of devices supported by VITAL libraries, thereby extending the use of VHDL into test program generation. Simulation driven VTest methodologies enable development of digital test programs completely off-line and with the ability to target virtually any digital ATE.","PeriodicalId":369132,"journal":{"name":"1997 IEEE Autotestcon Proceedings AUTOTESTCON '97. IEEE Systems Readiness Technology Conference. Systems Readiness Supporting Global Needs and Awareness in the 21st Century","volume":"49 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-09-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128169506","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-09-22DOI: 10.1109/AUTEST.1997.633677
M. Wright
VXI has matured into a flexible bus architecture with which to develop various types of instrumentation systems. More and more systems are being developed that require multiple chassis with dozens of instruments, each of which may perform a distinct yet important function to the system. This can place a tremendous burden on the system controller, especially if this same controller has to perform intensive graphic display updates, writes to the hard disk, printing functions, or other I/O Tasks. Modern computers in general, and PC-based computers in particular, have advanced to the point where some of this burden can be overcome by the sheer power of the processor. However, there are still many systems that would benefit from using a multi-computer approach. This paper details the multi-computer approach used in the VXIbased system that CACI developed for the Air Force. The system, the Engine Test/Trim Automated System II (ETTAS II) is designed to test all Air Force jet engines. The paper discusses how to integrate multiple computers in a VXI-based system, including discussions on: setting up the computers, selecting register-based versus message-based computers, setting up and using shared-memory, defining and separating tasks for each computer. The shared memory discussion talks about different ways to structure the shared memory, including setting up a system-level "Current-Value Table" (CVT) for all instruments, as well as how other devices, including another computer can access the shared memory space. The paper shows how Commercial Off-the-Shelf(COTS) software products NI-VXI LabVIEW; and NI-VISA (National Instruments) can be used to satisfy all these requirements. The paper also shows how the multi-computer approach can be cost-effective in many cases.
{"title":"Setting up and using a multi-computer VXIbus system","authors":"M. Wright","doi":"10.1109/AUTEST.1997.633677","DOIUrl":"https://doi.org/10.1109/AUTEST.1997.633677","url":null,"abstract":"VXI has matured into a flexible bus architecture with which to develop various types of instrumentation systems. More and more systems are being developed that require multiple chassis with dozens of instruments, each of which may perform a distinct yet important function to the system. This can place a tremendous burden on the system controller, especially if this same controller has to perform intensive graphic display updates, writes to the hard disk, printing functions, or other I/O Tasks. Modern computers in general, and PC-based computers in particular, have advanced to the point where some of this burden can be overcome by the sheer power of the processor. However, there are still many systems that would benefit from using a multi-computer approach. This paper details the multi-computer approach used in the VXIbased system that CACI developed for the Air Force. The system, the Engine Test/Trim Automated System II (ETTAS II) is designed to test all Air Force jet engines. The paper discusses how to integrate multiple computers in a VXI-based system, including discussions on: setting up the computers, selecting register-based versus message-based computers, setting up and using shared-memory, defining and separating tasks for each computer. The shared memory discussion talks about different ways to structure the shared memory, including setting up a system-level \"Current-Value Table\" (CVT) for all instruments, as well as how other devices, including another computer can access the shared memory space. The paper shows how Commercial Off-the-Shelf(COTS) software products NI-VXI LabVIEW; and NI-VISA (National Instruments) can be used to satisfy all these requirements. The paper also shows how the multi-computer approach can be cost-effective in many cases.","PeriodicalId":369132,"journal":{"name":"1997 IEEE Autotestcon Proceedings AUTOTESTCON '97. IEEE Systems Readiness Technology Conference. Systems Readiness Supporting Global Needs and Awareness in the 21st Century","volume":"118 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-09-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121602559","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1997-09-22DOI: 10.1109/AUTEST.1997.633675
D. Johnston, F. Shows
The United States Air Force (USAF) currently supports three (3) Jet/Turbo Prop/Gas turbine engine (GTE) test systems. The engine Test/Trim automated system (ETTAS) is used to accomplish field level testing. The pacer comet III (PC III) is used to perform depot level testing, and the automated ground engine test set (AGETS) is used for field level testing of F-100 engines. Each of these test systems is comprised of technologies which vary significantly in age and capability the USAF would prefer to have a single engine test system capable of meeting the requirements of all three of the existing test systems. The engine Test/Trim automated system II (ETTAS II) was designed to replace the existing ETTAS test system for the USAF. One of the design goals for ETTAS II was to provide an upgrade path which would allow the capabilities of the remaining two engine test systems to be incorporated. This paper describes the existing capabilities of ETTAS II, and details how the added requirements of the AGETS and PC III are accommodated. The requirements of the AGETS and PC III include automatic closed loop engine control and vibration signal acquisition and analysis. Additional switching capability, expanded discrete I/O, and a frequency source will also be added to the ETTAS II. The ETTAS II is comprised of commercial off the Shelf(COTS) hardware, and the additional capability added to the ETTAS II will be integrated using COTS equipment the ETTAS II was designed with enough "horsepower" to allow the incorporation of these additional functions without having and adverse impact on system performance.
{"title":"Automatic jet engine test system using commercial off the shelf (COTS) hardware and software platforms","authors":"D. Johnston, F. Shows","doi":"10.1109/AUTEST.1997.633675","DOIUrl":"https://doi.org/10.1109/AUTEST.1997.633675","url":null,"abstract":"The United States Air Force (USAF) currently supports three (3) Jet/Turbo Prop/Gas turbine engine (GTE) test systems. The engine Test/Trim automated system (ETTAS) is used to accomplish field level testing. The pacer comet III (PC III) is used to perform depot level testing, and the automated ground engine test set (AGETS) is used for field level testing of F-100 engines. Each of these test systems is comprised of technologies which vary significantly in age and capability the USAF would prefer to have a single engine test system capable of meeting the requirements of all three of the existing test systems. The engine Test/Trim automated system II (ETTAS II) was designed to replace the existing ETTAS test system for the USAF. One of the design goals for ETTAS II was to provide an upgrade path which would allow the capabilities of the remaining two engine test systems to be incorporated. This paper describes the existing capabilities of ETTAS II, and details how the added requirements of the AGETS and PC III are accommodated. The requirements of the AGETS and PC III include automatic closed loop engine control and vibration signal acquisition and analysis. Additional switching capability, expanded discrete I/O, and a frequency source will also be added to the ETTAS II. The ETTAS II is comprised of commercial off the Shelf(COTS) hardware, and the additional capability added to the ETTAS II will be integrated using COTS equipment the ETTAS II was designed with enough \"horsepower\" to allow the incorporation of these additional functions without having and adverse impact on system performance.","PeriodicalId":369132,"journal":{"name":"1997 IEEE Autotestcon Proceedings AUTOTESTCON '97. IEEE Systems Readiness Technology Conference. Systems Readiness Supporting Global Needs and Awareness in the 21st Century","volume":"58 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-09-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131946878","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
1997 IEEE Autotestcon Proceedings AUTOTESTCON '97. IEEE Systems Readiness Technology Conference. Systems Readiness Supporting Global Needs and Awareness in the 21st Century
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