{"title":"20nm低功耗三栅极多体1T-DRAM单元","authors":"F. Gámiz, N. Rodriguez, S. Cristoloveanu","doi":"10.1109/VLSI-TSA.2012.6210166","DOIUrl":null,"url":null,"abstract":"The new concept of Triple-Gate 1T-DRAM cell features N/P body partition that enables the physical separation of hole storage and electron current. The hole concentration controls the partial or full depletion of the N-core. The cell is compatible with ultimate scaling and shows attractive performance (long retention, wide memory window, simple programming, nondestructive reading, and very low-power operation) for embedded systems.","PeriodicalId":388574,"journal":{"name":"Proceedings of Technical Program of 2012 VLSI Technology, System and Application","volume":"119 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2012-04-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":"{\"title\":\"A 20nm low-power triple-gate multibody 1T-DRAM cell\",\"authors\":\"F. Gámiz, N. Rodriguez, S. Cristoloveanu\",\"doi\":\"10.1109/VLSI-TSA.2012.6210166\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"The new concept of Triple-Gate 1T-DRAM cell features N/P body partition that enables the physical separation of hole storage and electron current. The hole concentration controls the partial or full depletion of the N-core. The cell is compatible with ultimate scaling and shows attractive performance (long retention, wide memory window, simple programming, nondestructive reading, and very low-power operation) for embedded systems.\",\"PeriodicalId\":388574,\"journal\":{\"name\":\"Proceedings of Technical Program of 2012 VLSI Technology, System and Application\",\"volume\":\"119 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2012-04-23\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"1\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings of Technical Program of 2012 VLSI Technology, System and Application\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/VLSI-TSA.2012.6210166\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings of Technical Program of 2012 VLSI Technology, System and Application","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/VLSI-TSA.2012.6210166","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A 20nm low-power triple-gate multibody 1T-DRAM cell
The new concept of Triple-Gate 1T-DRAM cell features N/P body partition that enables the physical separation of hole storage and electron current. The hole concentration controls the partial or full depletion of the N-core. The cell is compatible with ultimate scaling and shows attractive performance (long retention, wide memory window, simple programming, nondestructive reading, and very low-power operation) for embedded systems.
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