{"title":"用多值电压比较器实现NMAX和NMIN函数","authors":"M. Inaba, K. Tanno, O. Ishizuka","doi":"10.1109/ISMVL.2001.924551","DOIUrl":null,"url":null,"abstract":"In this paper, realization of three fundamental functions, NOT, negated MAX and negated MIN functions, in the voltage-mode quaternary logic is presented. First, the high-performance NOT circuits with the down literal circuits are composed. The proposed NOT circuits have the quantified effect to realize high noise margins in the voltage-mode quaternary logic circuits. Next, we propose the voltage comparator with the NOT circuit, and, as applications of the voltage comparator, NMAX and NMIN circuits are designed. They can realize the negated MAX and the negated MIN functions, respectively. The advantages of these proposed circuits are fabrication with a conventional CMOS process, high noise margins of more than 0.46[V] and low power consumption with peak of less than 350[/spl mu/W] under 3.0[V] of the supply voltage in verification using HSPICE simulations.","PeriodicalId":297353,"journal":{"name":"Proceedings 31st IEEE International Symposium on Multiple-Valued Logic","volume":"5 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2001-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"20","resultStr":"{\"title\":\"Realization of NMAX and NMIN functions with multi-valued voltage comparators\",\"authors\":\"M. Inaba, K. Tanno, O. Ishizuka\",\"doi\":\"10.1109/ISMVL.2001.924551\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"In this paper, realization of three fundamental functions, NOT, negated MAX and negated MIN functions, in the voltage-mode quaternary logic is presented. First, the high-performance NOT circuits with the down literal circuits are composed. The proposed NOT circuits have the quantified effect to realize high noise margins in the voltage-mode quaternary logic circuits. Next, we propose the voltage comparator with the NOT circuit, and, as applications of the voltage comparator, NMAX and NMIN circuits are designed. They can realize the negated MAX and the negated MIN functions, respectively. The advantages of these proposed circuits are fabrication with a conventional CMOS process, high noise margins of more than 0.46[V] and low power consumption with peak of less than 350[/spl mu/W] under 3.0[V] of the supply voltage in verification using HSPICE simulations.\",\"PeriodicalId\":297353,\"journal\":{\"name\":\"Proceedings 31st IEEE International Symposium on Multiple-Valued Logic\",\"volume\":\"5 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2001-05-22\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"20\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings 31st IEEE International Symposium on Multiple-Valued Logic\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ISMVL.2001.924551\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings 31st IEEE International Symposium on Multiple-Valued Logic","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISMVL.2001.924551","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Realization of NMAX and NMIN functions with multi-valued voltage comparators
In this paper, realization of three fundamental functions, NOT, negated MAX and negated MIN functions, in the voltage-mode quaternary logic is presented. First, the high-performance NOT circuits with the down literal circuits are composed. The proposed NOT circuits have the quantified effect to realize high noise margins in the voltage-mode quaternary logic circuits. Next, we propose the voltage comparator with the NOT circuit, and, as applications of the voltage comparator, NMAX and NMIN circuits are designed. They can realize the negated MAX and the negated MIN functions, respectively. The advantages of these proposed circuits are fabrication with a conventional CMOS process, high noise margins of more than 0.46[V] and low power consumption with peak of less than 350[/spl mu/W] under 3.0[V] of the supply voltage in verification using HSPICE simulations.