Pub Date : 2001-05-22DOI: 10.1109/ISMVL.2001.924560
T. Waho, K. Hattori, Y. Takamatsu
We have proposed a flash analog-to-digital converter (ADC) that uses resonant-tunneling complex gates not only as ternary quantizers but also as ternary-to-binary encoder circuits. The ternary quantizers, consisting of monostable-to-multistable transition logic (MML) circuits, convert the analog input signal into the ternary thermometer code. This code is then converted into the binary Gray-code output by a multiple-valued, multiple-input monostable-to-bistable transition logic element (M/sup 2/-MOBILE). By assuming InP-based resonant-tunneling diodes and heterojunction field-effect transistors, we have carried out SPICE simulation that demonstrates ultrahigh-speed ADC operation at a clock frequency of 5 GHz. Compact circuit configuration, which is due to the combination of MML and M/sup 2/-MOBILE, reduces the device count and power dissipation by a factor of two compared with previous RTD-based ADCs.
{"title":"Flash analog-to-digital converter using resonant-tunneling multiple-valued circuits","authors":"T. Waho, K. Hattori, Y. Takamatsu","doi":"10.1109/ISMVL.2001.924560","DOIUrl":"https://doi.org/10.1109/ISMVL.2001.924560","url":null,"abstract":"We have proposed a flash analog-to-digital converter (ADC) that uses resonant-tunneling complex gates not only as ternary quantizers but also as ternary-to-binary encoder circuits. The ternary quantizers, consisting of monostable-to-multistable transition logic (MML) circuits, convert the analog input signal into the ternary thermometer code. This code is then converted into the binary Gray-code output by a multiple-valued, multiple-input monostable-to-bistable transition logic element (M/sup 2/-MOBILE). By assuming InP-based resonant-tunneling diodes and heterojunction field-effect transistors, we have carried out SPICE simulation that demonstrates ultrahigh-speed ADC operation at a clock frequency of 5 GHz. Compact circuit configuration, which is due to the combination of MML and M/sup 2/-MOBILE, reduces the device count and power dissipation by a factor of two compared with previous RTD-based ADCs.","PeriodicalId":297353,"journal":{"name":"Proceedings 31st IEEE International Symposium on Multiple-Valued Logic","volume":"70 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115232493","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2001-05-22DOI: 10.1109/ISMVL.2001.924590
P. Hájek, Z. Haniková
This paper proposes a possibility of developing an axiomatic set theory, as first-order theory within the framework of fuzzy logic in the style of Hajek's Basic fuzzy logic BL. In classical Zermelo-Fraenkel set theory, we use an analogy of the construction of a Boolean-valued universe-over a particular algebra of truth values-we show the nontriviality of our theory. We present a list of problems and research tasks.
{"title":"A set theory within fuzzy logic","authors":"P. Hájek, Z. Haniková","doi":"10.1109/ISMVL.2001.924590","DOIUrl":"https://doi.org/10.1109/ISMVL.2001.924590","url":null,"abstract":"This paper proposes a possibility of developing an axiomatic set theory, as first-order theory within the framework of fuzzy logic in the style of Hajek's Basic fuzzy logic BL. In classical Zermelo-Fraenkel set theory, we use an analogy of the construction of a Boolean-valued universe-over a particular algebra of truth values-we show the nontriviality of our theory. We present a list of problems and research tasks.","PeriodicalId":297353,"journal":{"name":"Proceedings 31st IEEE International Symposium on Multiple-Valued Logic","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117215919","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2001-05-22DOI: 10.1109/ISMVL.2001.924572
D. V. Heule, A. Hoogewijs
In this paper, we explain the use of PPC NAT, a three-valued first-order object logic (PPC) implemented in Isabelle, for reasoning with undefined expressions. This kind of expressions can be found in default logic where deductions are divided from facts (which are true) together with a set of assumptions (defaults), which can be true. The main features of our system are: the ability to formalize default assumptions and to reason about them automatically.
{"title":"Automated reasoning with ordinary assertions and default assumptions","authors":"D. V. Heule, A. Hoogewijs","doi":"10.1109/ISMVL.2001.924572","DOIUrl":"https://doi.org/10.1109/ISMVL.2001.924572","url":null,"abstract":"In this paper, we explain the use of PPC NAT, a three-valued first-order object logic (PPC) implemented in Isabelle, for reasoning with undefined expressions. This kind of expressions can be found in default logic where deductions are divided from facts (which are true) together with a set of assumptions (defaults), which can be true. The main features of our system are: the ability to formalize default assumptions and to reason about them automatically.","PeriodicalId":297353,"journal":{"name":"Proceedings 31st IEEE International Symposium on Multiple-Valued Logic","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131009749","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2001-05-22DOI: 10.1109/ISMVL.2001.924577
A. Ciabattoni, C. Fermüller
We summarize various results in proof theory of many-valued and related logics that jointly clarify the relations between important logics like MTL, (different versions of) Urquhart's C, contraction-free versions of intuitionistic logic, and Godel logic. The central tool of investigation is the embedding of suitable sequent calculi into hypersequent calculi that include Avron's communication rule.
{"title":"Hypersequents as a uniform framework for Urquhart's C, MTL and related logics","authors":"A. Ciabattoni, C. Fermüller","doi":"10.1109/ISMVL.2001.924577","DOIUrl":"https://doi.org/10.1109/ISMVL.2001.924577","url":null,"abstract":"We summarize various results in proof theory of many-valued and related logics that jointly clarify the relations between important logics like MTL, (different versions of) Urquhart's C, contraction-free versions of intuitionistic logic, and Godel logic. The central tool of investigation is the embedding of suitable sequent calculi into hypersequent calculi that include Avron's communication rule.","PeriodicalId":297353,"journal":{"name":"Proceedings 31st IEEE International Symposium on Multiple-Valued Logic","volume":"191 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133446320","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2001-05-22DOI: 10.1109/ISMVL.2001.924559
T. Uemura, T. Baba
A three-valued D-flip-flop (D-FF) circuit and a two-stage shift register built from InGaAs-based multiple-junction surface tunnel transistors (MJSTT) and Si-based metal-oxide-semiconductor field effect transistors (MOSFET) have been demonstrated. Due to the combination of the MJSTT's latching function and the MOSFET's switching function, the number of devices required for the D-FF circuit was greatly reduced to two from the thirty required for the FET-only circuit.
{"title":"A three-valued D-flip-flop and shift register using multiple-junction surface tunnel transistors","authors":"T. Uemura, T. Baba","doi":"10.1109/ISMVL.2001.924559","DOIUrl":"https://doi.org/10.1109/ISMVL.2001.924559","url":null,"abstract":"A three-valued D-flip-flop (D-FF) circuit and a two-stage shift register built from InGaAs-based multiple-junction surface tunnel transistors (MJSTT) and Si-based metal-oxide-semiconductor field effect transistors (MOSFET) have been demonstrated. Due to the combination of the MJSTT's latching function and the MOSFET's switching function, the number of devices required for the D-FF circuit was greatly reduced to two from the thirty required for the FET-only circuit.","PeriodicalId":297353,"journal":{"name":"Proceedings 31st IEEE International Symposium on Multiple-Valued Logic","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125646491","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2001-05-22DOI: 10.1109/ISMVL.2001.924578
S. Selezneva
The aim of this paper is to present a general approach to designing efficient algorithms intended for checking some properties (monotonicity, some specific variants of precompleteness, etc.) of multiple-valued functions represented by polynomials. The properties under consideration are characterized by predicates. The key idea of this approach is based upon the extension of the concept of transitivity to predicates of arbitrary arity. We demonstrate that whenever multiple-valued functions are represented by polynomials and some set of functions is characterized by an extended transitive and total reflexive predicate, then the membership problem for this class is decidable in polynomial time.
{"title":"Polynomial-time algorithms for verification of some properties of k-valued functions represented by polynomials","authors":"S. Selezneva","doi":"10.1109/ISMVL.2001.924578","DOIUrl":"https://doi.org/10.1109/ISMVL.2001.924578","url":null,"abstract":"The aim of this paper is to present a general approach to designing efficient algorithms intended for checking some properties (monotonicity, some specific variants of precompleteness, etc.) of multiple-valued functions represented by polynomials. The properties under consideration are characterized by predicates. The key idea of this approach is based upon the extension of the concept of transitivity to predicates of arbitrary arity. We demonstrate that whenever multiple-valued functions are represented by polynomials and some set of functions is characterized by an extended transitive and total reflexive predicate, then the membership problem for this class is decidable in polynomial time.","PeriodicalId":297353,"journal":{"name":"Proceedings 31st IEEE International Symposium on Multiple-Valued Logic","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132967862","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2001-05-22DOI: 10.1109/ISMVL.2001.924588
R. Stankovic, M. Stankovic, J. Astola, K. Egiazarian
In this paper, we extend various Boolean representations for switching functions, as SOPs, Reed-Muller expressions, Kronecker and Pseudo Kronecker ANDEXOR expressions, to functions used in Fibonacci interconnection topologies. Then, we extend the world-level expressions, as arithmetic expressions, and Walsh expressions, to these functions. We introduce the corresponding decision diagrams as graphic representations of these bit-level and word-level expressions. In this way, we provide a base to extend the application of powerful CAD design tools using polynomial expressions and DDs for switching functions to functions in Fibonacci interconnection topologies.
在本文中，我们将交换函数的各种布尔表示，如SOPs, Reed-Muller表达式，Kronecker和Pseudo Kronecker and dexor表达式，扩展到Fibonacci互连拓扑中使用的函数。然后，我们将世界级表达式(如算术表达式和Walsh表达式)扩展到这些函数。我们引入相应的决策图作为这些位级和字级表达式的图形表示。通过这种方式，我们提供了一个基础来扩展功能强大的CAD设计工具的应用，使用多项式表达式和dd将函数转换为斐波那契互连拓扑中的函数。
{"title":"Bit-level and word-level polynomial expressions for functions in Fibonacci interconnection topologies","authors":"R. Stankovic, M. Stankovic, J. Astola, K. Egiazarian","doi":"10.1109/ISMVL.2001.924588","DOIUrl":"https://doi.org/10.1109/ISMVL.2001.924588","url":null,"abstract":"In this paper, we extend various Boolean representations for switching functions, as SOPs, Reed-Muller expressions, Kronecker and Pseudo Kronecker ANDEXOR expressions, to functions used in Fibonacci interconnection topologies. Then, we extend the world-level expressions, as arithmetic expressions, and Walsh expressions, to these functions. We introduce the corresponding decision diagrams as graphic representations of these bit-level and word-level expressions. In this way, we provide a base to extend the application of powerful CAD design tools using polynomial expressions and DDs for switching functions to functions in Fibonacci interconnection topologies.","PeriodicalId":297353,"journal":{"name":"Proceedings 31st IEEE International Symposium on Multiple-Valued Logic","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122707779","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2001-05-22DOI: 10.1109/ISMVL.2001.924595
Q. Hua, Q.-L. Zhen
The Fuzzy Neural Hamming Classifier (FNHC) can resolve the pattern overlap with the degree of fuzzy class membership; ensure the convergence and decrease the interconnection with the comparison subnet; accept both binary and non-binary input. Using only integer threshold and weights, FNHC is easily implemented in VLSI technology.
{"title":"The designing and training of a fuzzy neural Hamming classifier","authors":"Q. Hua, Q.-L. Zhen","doi":"10.1109/ISMVL.2001.924595","DOIUrl":"https://doi.org/10.1109/ISMVL.2001.924595","url":null,"abstract":"The Fuzzy Neural Hamming Classifier (FNHC) can resolve the pattern overlap with the degree of fuzzy class membership; ensure the convergence and decrease the interconnection with the comparison subnet; accept both binary and non-binary input. Using only integer threshold and weights, FNHC is easily implemented in VLSI technology.","PeriodicalId":297353,"journal":{"name":"Proceedings 31st IEEE International Symposium on Multiple-Valued Logic","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127703061","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2001-05-22DOI: 10.1109/ISMVL.2001.924562
Evren Gürkan, A. Erkmen, I. Erkmen
Our objective in this paper is to evaluate inconsistency for our proposed 2-way fuzzy adaptive system that makes use of intuitionistic fuzzy sets. Uncertainty is modeled as the width of the interval introduced by the independent assignment of membership and nonmembership functions of the intuitionistic fuzzy sets. There is only a consistency constrain in this assignment, violation of which gives rise to inconsistency in the system. The inconsistency model using this fact is reduced through training. There are two phases of training for our proposed 2-way adaptive fuzzy system. The evaluation of the degree of reduction of inconsistency is carried out at the end of phase 1 training by forming the shadowed set patterns of the membership and nonmembership functions after training. The shadowed set patterns are first mapped into types of inconsistencies which are further classified according to the global index of fuzziness generated out of the output membership and nonmembership functions. It is seen that the system is able to reduce inconsistency very efficiently.
{"title":"Evaluation of inconsistency in a 2-way fuzzy adaptive system using shadowed sets","authors":"Evren Gürkan, A. Erkmen, I. Erkmen","doi":"10.1109/ISMVL.2001.924562","DOIUrl":"https://doi.org/10.1109/ISMVL.2001.924562","url":null,"abstract":"Our objective in this paper is to evaluate inconsistency for our proposed 2-way fuzzy adaptive system that makes use of intuitionistic fuzzy sets. Uncertainty is modeled as the width of the interval introduced by the independent assignment of membership and nonmembership functions of the intuitionistic fuzzy sets. There is only a consistency constrain in this assignment, violation of which gives rise to inconsistency in the system. The inconsistency model using this fact is reduced through training. There are two phases of training for our proposed 2-way adaptive fuzzy system. The evaluation of the degree of reduction of inconsistency is carried out at the end of phase 1 training by forming the shadowed set patterns of the membership and nonmembership functions after training. The shadowed set patterns are first mapped into types of inconsistencies which are further classified according to the global index of fuzziness generated out of the output membership and nonmembership functions. It is seen that the system is able to reduce inconsistency very efficiently.","PeriodicalId":297353,"journal":{"name":"Proceedings 31st IEEE International Symposium on Multiple-Valued Logic","volume":"40 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115030954","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2001-05-22DOI: 10.1109/ISMVL.2001.924594
H. Tatsumi, Y. Murai, S. Tokumasu
This paper presents a new method of logic diagnosis for combinatorial logic circuits. First, for each type of circuit gates, an equivalent neural network gate is constructed. Then, by replacing circuit gate elements with corresponding neural network gates, an equivalent neural network circuit is constructed to the fault-free sample circuit. The testing procedure is to feed random patterns to both the neural network circuit and the fault-prone test circuit at the same time, and comparing, analyzing both outputs, the former circuit generates diagnostic data for the test circuit. Thus, the neural network circuit behaves like a diagnostic engine, and needs basically no preparation of special test patterns nor fault dictionary before diagnosing.
{"title":"Logic circuit diagnosis by using neural networks","authors":"H. Tatsumi, Y. Murai, S. Tokumasu","doi":"10.1109/ISMVL.2001.924594","DOIUrl":"https://doi.org/10.1109/ISMVL.2001.924594","url":null,"abstract":"This paper presents a new method of logic diagnosis for combinatorial logic circuits. First, for each type of circuit gates, an equivalent neural network gate is constructed. Then, by replacing circuit gate elements with corresponding neural network gates, an equivalent neural network circuit is constructed to the fault-free sample circuit. The testing procedure is to feed random patterns to both the neural network circuit and the fault-prone test circuit at the same time, and comparing, analyzing both outputs, the former circuit generates diagnostic data for the test circuit. Thus, the neural network circuit behaves like a diagnostic engine, and needs basically no preparation of special test patterns nor fault dictionary before diagnosing.","PeriodicalId":297353,"journal":{"name":"Proceedings 31st IEEE International Symposium on Multiple-Valued Logic","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114368117","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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