一个2.7Gbps和1.62Gbps双模时钟和数据恢复用于0.18μm CMOS的DisplayPort

2009 IEEE International SOC Conference (SOCC) Pub Date : 2009-09-01 DOI:10.1109/SOCCON.2009.5398064

Seungwon Lee, Tae-Ho Kim, Jae-Wook Yoo, Jin-Ku Kang

{"title":"一个2.7Gbps和1.62Gbps双模时钟和数据恢复用于0.18μm CMOS的DisplayPort","authors":"Seungwon Lee, Tae-Ho Kim, Jae-Wook Yoo, Jin-Ku Kang","doi":"10.1109/SOCCON.2009.5398064","DOIUrl":null,"url":null,"abstract":"This paper describes a clock and data recovery (CDR) circuit that support dual data rates of 2.7Gbps and 1.62Gbps for DisplayPort standard. The proposed CDR has a dual mode voltage-controlled oscillator (VCO) that changes the operating frequency with a “Mode” switch control. The chip has been implemented using 0.18μm CMOS process. Measured results show the circuit exhibits peak-to-peak jitters of 37ps(@2.7Gbps) and 27ps(@1.62Gbps) in the recovered data. The power dissipation is 80mW at 2.7Gbps rate from a 1.8V supply.","PeriodicalId":303505,"journal":{"name":"2009 IEEE International SOC Conference (SOCC)","volume":"131 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2009-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":"{\"title\":\"A 2.7Gbps & 1.62Gbps dual-mode clock and data recovery for DisplayPort in 0.18μm CMOS\",\"authors\":\"Seungwon Lee, Tae-Ho Kim, Jae-Wook Yoo, Jin-Ku Kang\",\"doi\":\"10.1109/SOCCON.2009.5398064\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper describes a clock and data recovery (CDR) circuit that support dual data rates of 2.7Gbps and 1.62Gbps for DisplayPort standard. The proposed CDR has a dual mode voltage-controlled oscillator (VCO) that changes the operating frequency with a “Mode” switch control. The chip has been implemented using 0.18μm CMOS process. Measured results show the circuit exhibits peak-to-peak jitters of 37ps(@2.7Gbps) and 27ps(@1.62Gbps) in the recovered data. The power dissipation is 80mW at 2.7Gbps rate from a 1.8V supply.\",\"PeriodicalId\":303505,\"journal\":{\"name\":\"2009 IEEE International SOC Conference (SOCC)\",\"volume\":\"131 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2009-09-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"1\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2009 IEEE International SOC Conference (SOCC)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/SOCCON.2009.5398064\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2009 IEEE International SOC Conference (SOCC)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/SOCCON.2009.5398064","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}

引用次数: 1

摘要

本文介绍了一种时钟和数据恢复(CDR)电路，该电路支持2.7Gbps和1.62Gbps的双数据速率。提出的CDR具有双模压控振荡器(VCO)，通过“模式”开关控制改变工作频率。该芯片采用0.18μm CMOS工艺实现。测量结果显示，电路在恢复的数据中显示出37ps(@2.7Gbps)和27ps(@1.62Gbps)的峰值抖动。功耗为80mW, 2.7Gbps速率，1.8V电源。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

查看原文

微信好友朋友圈 QQ好友复制链接

本刊更多论文

A 2.7Gbps & 1.62Gbps dual-mode clock and data recovery for DisplayPort in 0.18μm CMOS

This paper describes a clock and data recovery (CDR) circuit that support dual data rates of 2.7Gbps and 1.62Gbps for DisplayPort standard. The proposed CDR has a dual mode voltage-controlled oscillator (VCO) that changes the operating frequency with a “Mode” switch control. The chip has been implemented using 0.18μm CMOS process. Measured results show the circuit exhibits peak-to-peak jitters of 37ps(@2.7Gbps) and 27ps(@1.62Gbps) in the recovered data. The power dissipation is 80mW at 2.7Gbps rate from a 1.8V supply.

求助全文

通过发布文献求助，成功后即可免费获取论文全文。去求助

来源期刊

2009 IEEE International SOC Conference (SOCC)

自引率

0.00%

发文量