M. Aberbour, H. Mehrez, F. Durbin, J. Haussy, P. Lalande, A. Tissot
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A system-on-a-chip for pattern recognition architecture and design methodology
We address in this paper the design and specification of a heterogeneous architecture of a SOC (System-On-a-Chip) for pattern recognition. Once the algorithms involved presented, we investigate the hardware/software codesign methodology, the system architecture and finally the VLSI physical integration. We conclude by giving results on the performance of the system regarding recognition rate and VLSI characteristics.
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