{"title":"单芯片宽带CMOS功率放大器和跟踪器,总效率为37%,适用于TDD/FDD LTE应用","authors":"F. Balteanu","doi":"10.1109/RFIC.2016.7508316","DOIUrl":null,"url":null,"abstract":"This paper presents a 2.3GHz - 2.7GHz broadband CMOS FDD/TDD LTE Band 7. 38, 40 and 41 power amplifier (PA) fully integrated with a fast envelope tracker (ET) on a single 0.18μm CMOS die. The PA and the tracker achieve a 37% overall efficiency for 26.5dBm and -39dBc ACLR1. The entire design including the input/output match uses an active silicon area around 2.7mm2.","PeriodicalId":163595,"journal":{"name":"2016 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)","volume":"194 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2016-05-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"2","resultStr":"{\"title\":\"Single die broadband CMOS power amplifier and tracker with 37% overall efficiency for TDD/FDD LTE applications\",\"authors\":\"F. Balteanu\",\"doi\":\"10.1109/RFIC.2016.7508316\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This paper presents a 2.3GHz - 2.7GHz broadband CMOS FDD/TDD LTE Band 7. 38, 40 and 41 power amplifier (PA) fully integrated with a fast envelope tracker (ET) on a single 0.18μm CMOS die. The PA and the tracker achieve a 37% overall efficiency for 26.5dBm and -39dBc ACLR1. The entire design including the input/output match uses an active silicon area around 2.7mm2.\",\"PeriodicalId\":163595,\"journal\":{\"name\":\"2016 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)\",\"volume\":\"194 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2016-05-22\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"2\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2016 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/RFIC.2016.7508316\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2016 IEEE Radio Frequency Integrated Circuits Symposium (RFIC)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/RFIC.2016.7508316","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 2
摘要
本文提出了一种2.3GHz - 2.7GHz宽带CMOS FDD/TDD LTE Band 7。38、40和41功率放大器(PA)与快速包络跟踪器(ET)完全集成在单个0.18μm CMOS芯片上。PA和跟踪器在26.5dBm和-39dBc ACLR1下实现37%的总效率。整个设计包括输入/输出匹配使用约2.7mm2的有源硅面积。
Single die broadband CMOS power amplifier and tracker with 37% overall efficiency for TDD/FDD LTE applications
This paper presents a 2.3GHz - 2.7GHz broadband CMOS FDD/TDD LTE Band 7. 38, 40 and 41 power amplifier (PA) fully integrated with a fast envelope tracker (ET) on a single 0.18μm CMOS die. The PA and the tracker achieve a 37% overall efficiency for 26.5dBm and -39dBc ACLR1. The entire design including the input/output match uses an active silicon area around 2.7mm2.