Low power CMOS digital circuit design methodologies with reduced voltage swing

In this paper, two techniques on low power circuit design, namely, clock separated logic and sub-V/sub dd/ voltage-swing interfacing, are introduced. In the former method, reduced voltage-swing at internal nodes is used to achieve relatively low power dissipation as compared to circuits with full voltage-swing. In the latter method, pass-transistor logic with suppressed internal voltage-swing is used to reduce power dissipation in the pass-transistor chain. Basic techniques on design of these circuits are investigated and analyzed.