SRAM oriented memory sense amplifier design in 0.18 /spl mu/m CMOS technology

In this paper a new two-stage sensing scheme suitable for current sensing in SRAM read operation is presented. The proposed scheme provides fast response with low silicon area requirements, since it incorporates only three transistors in the pitch of the bit lines for the sensing of the stored data in the selected memory cell. Process and temperature variation related simulations are provided in order to explore the operating range of the sensors in various conditions. In addition, comparison results are given with respect to a conventional sensing scheme. Finally, a compact layout design is presented to illustrate the area efficiency of the proposed sensing architecture.