{"title":"级联载波选择加法器(C/sup 2/SA):一种用于低功耗载波选择加法器设计的新结构","authors":"Yiran Chen, Hai Helen Li, K. Roy, Cheng-Kok Koh","doi":"10.1145/1077603.1077634","DOIUrl":null,"url":null,"abstract":"In this paper we propose a novel low-power carry-select adder (CSA) design called cascaded CSA (C/sup 2/SA). Based on the prediction of the critical path delay of current operation, C/sup 2/SA can automatically work with one or two clock-cycle latency and a scaled supply voltage to achieve power improvement. Post-layout simulations of a 64-bit C/sup 2/SA in 180nm technology show that C/sup 2/SA can operate at a lower supply voltage, attaining 40.7% energy saving, while maintaining a similar (average) latency per operation (LPO) compared to standard CSA.","PeriodicalId":256018,"journal":{"name":"ISLPED '05. Proceedings of the 2005 International Symposium on Low Power Electronics and Design, 2005.","volume":"23 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2005-08-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"14","resultStr":"{\"title\":\"Cascaded carry-select adder (C/sup 2/SA): a new structure for low-power CSA design\",\"authors\":\"Yiran Chen, Hai Helen Li, K. Roy, Cheng-Kok Koh\",\"doi\":\"10.1145/1077603.1077634\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"In this paper we propose a novel low-power carry-select adder (CSA) design called cascaded CSA (C/sup 2/SA). Based on the prediction of the critical path delay of current operation, C/sup 2/SA can automatically work with one or two clock-cycle latency and a scaled supply voltage to achieve power improvement. Post-layout simulations of a 64-bit C/sup 2/SA in 180nm technology show that C/sup 2/SA can operate at a lower supply voltage, attaining 40.7% energy saving, while maintaining a similar (average) latency per operation (LPO) compared to standard CSA.\",\"PeriodicalId\":256018,\"journal\":{\"name\":\"ISLPED '05. Proceedings of the 2005 International Symposium on Low Power Electronics and Design, 2005.\",\"volume\":\"23 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2005-08-08\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"14\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"ISLPED '05. Proceedings of the 2005 International Symposium on Low Power Electronics and Design, 2005.\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1145/1077603.1077634\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"ISLPED '05. Proceedings of the 2005 International Symposium on Low Power Electronics and Design, 2005.","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1145/1077603.1077634","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Cascaded carry-select adder (C/sup 2/SA): a new structure for low-power CSA design
In this paper we propose a novel low-power carry-select adder (CSA) design called cascaded CSA (C/sup 2/SA). Based on the prediction of the critical path delay of current operation, C/sup 2/SA can automatically work with one or two clock-cycle latency and a scaled supply voltage to achieve power improvement. Post-layout simulations of a 64-bit C/sup 2/SA in 180nm technology show that C/sup 2/SA can operate at a lower supply voltage, attaining 40.7% energy saving, while maintaining a similar (average) latency per operation (LPO) compared to standard CSA.
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