Proposal for fast BCD addition

Decimal Arithmetic Hardware Research accelerated phenomenally in the last decade with introduction of Decimal Floating Point formats in IEEE 754–2008. ‘Addition’ being one of the primitive arithmetic operations has attracted numerous literary proposals involving the 8421 standard BCD code as well as nonstandard decimal digit representation codes (4221, 5211 etc.). This paper concentrates on Fixed Point Addition and introduces two decimal adder designs; Design D1 and D2. D1 exhibits a novel Single Digit Fast BCD Adder adding two single digit BCD operands generating a valid double BCD result. Cascade of D1 forms D2, generating Two 16 Digit Operand Word Wide Adder. D1 theoretically lags behind the conventional BCD Adder by mere three gate level delays whereas D2 radically outperforms the conventional counterpart. We have performed theoretical logic level delay calculations and FPGA implementations which supporting the theoretical results. D2 has been compared with a literary counterpart and found to excel.