N. M. Madani, B. Tavassoli, A. Behnam, A. Afzali-Kusha
{"title":"栅极漏电流存在下的超截止CMOS技术研究","authors":"N. M. Madani, B. Tavassoli, A. Behnam, A. Afzali-Kusha","doi":"10.1109/ICM.2004.1434196","DOIUrl":null,"url":null,"abstract":"Super cut-off method as a well-known technique to reduce leakage power is investigated for its operational characteristics in the sub 100 nm technology nodes. Specially, the effect of the gate leakage in power consumption is considered and a design routine for optimizing the circuit in this regard is proposed. A right design methodology can improve the power and the circuit performance efficiently.","PeriodicalId":359193,"journal":{"name":"Proceedings. The 16th International Conference on Microelectronics, 2004. ICM 2004.","volume":"22 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2004-12-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"5","resultStr":"{\"title\":\"Study of super cut-off CMOS technique in presence of the gate leakage current\",\"authors\":\"N. M. Madani, B. Tavassoli, A. Behnam, A. Afzali-Kusha\",\"doi\":\"10.1109/ICM.2004.1434196\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Super cut-off method as a well-known technique to reduce leakage power is investigated for its operational characteristics in the sub 100 nm technology nodes. Specially, the effect of the gate leakage in power consumption is considered and a design routine for optimizing the circuit in this regard is proposed. A right design methodology can improve the power and the circuit performance efficiently.\",\"PeriodicalId\":359193,\"journal\":{\"name\":\"Proceedings. The 16th International Conference on Microelectronics, 2004. ICM 2004.\",\"volume\":\"22 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2004-12-06\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"5\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings. The 16th International Conference on Microelectronics, 2004. ICM 2004.\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ICM.2004.1434196\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings. The 16th International Conference on Microelectronics, 2004. ICM 2004.","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICM.2004.1434196","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Study of super cut-off CMOS technique in presence of the gate leakage current
Super cut-off method as a well-known technique to reduce leakage power is investigated for its operational characteristics in the sub 100 nm technology nodes. Specially, the effect of the gate leakage in power consumption is considered and a design routine for optimizing the circuit in this regard is proposed. A right design methodology can improve the power and the circuit performance efficiently.
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