A 32nm, 0.65–10GHz, 0.9/0.3 ps/σ TX/RX jitter single inductor digital fractional-n clock generator for reconfigurable serial I/O

In CPU, SOC, GPU, and PC-on-chip, I/O power consumption can be significant. To improve power efficiency, I/O bundles in group of 4, 8, or 16b, should scale their data rate according to the application requirements. However, clocking architecture imposes significant challenges to support different data rate simultaneously. In high bandwidth I/O, LC oscillators are preferred for low jitter, but the limited frequency range confines the data rate tuning. Multiple LC-PLLs are costly in area and power, and sometimes infeasible due to heavily congested I/O area. Worse still, couplings between inductors could lead to PLL pulling closing the sampling eye. In this paper, a reconfigurable 0.65–10GHz digital fractional-n clock generator using a single LC PLL, calibrated 0.75/1.25/1.75 digital fractional post dividers for serial I/O is presented. The architecture enables I/O driven by the same PLL to operate at different data rate, thereby reducing power. In addition, multiple LC-PLLs are replaced by one saving area, power, and coupling between LC oscillators. The PLL incorporates a staggered varactor, wide-tuning VCO, and a hysteretic redundant frequency acquisition for improved temperature stability. The prototype in a 32nm high-k metal gate process has a measured TX/RX jitter of 0.9/0.3 ps/σ and dissipates 36.2mW from 1.05V supply.