Pub Date : 2017-08-11DOI: 10.1109/ISLPED.2017.8009205
Ming-Hung Chien, Yen-Long Lee, J. Goh, Soon-Jyh Chang
This paper presents a novel low power duobinary voltage mode transmitter in 90-nm CMOS process for wireline communication. As a matter of fact, voltage mode transmitters potentially save much more power than current mode transmitters. By adding a medium level, a half supply voltage, to conventional NRZ voltage mode transmitters, duobinary coding can simply be achieved. Post-layout simulation demonstrates the architecture with a new preemphasis method dissipates approximately 16.35 mW from a 1.0 V supply when transmitting 8 Gb/s 1.0 V differential amplitude data with 2-tap pre-emphasis, achieving 2.04 pJ/bit energy efficiency.
{"title":"A low power duobinary voltage mode transmitter","authors":"Ming-Hung Chien, Yen-Long Lee, J. Goh, Soon-Jyh Chang","doi":"10.1109/ISLPED.2017.8009205","DOIUrl":"https://doi.org/10.1109/ISLPED.2017.8009205","url":null,"abstract":"This paper presents a novel low power duobinary voltage mode transmitter in 90-nm CMOS process for wireline communication. As a matter of fact, voltage mode transmitters potentially save much more power than current mode transmitters. By adding a medium level, a half supply voltage, to conventional NRZ voltage mode transmitters, duobinary coding can simply be achieved. Post-layout simulation demonstrates the architecture with a new preemphasis method dissipates approximately 16.35 mW from a 1.0 V supply when transmitting 8 Gb/s 1.0 V differential amplitude data with 2-tap pre-emphasis, achieving 2.04 pJ/bit energy efficiency.","PeriodicalId":385714,"journal":{"name":"2017 IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2017-08-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134339691","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-07-24DOI: 10.1109/ISLPED.2017.8009152
G. Rincón-Mora
A fundamental challenge wireless microsystems face is size, and in consequence, lifetime because tiny batteries exhaust quickly. Although small fuel cells and atomic sources store more energy than lithium-ion batteries and super capacitors, they source less power, so they cannot power as many functions. Small batteries and capacitors, however, cannot sustain life for long. Thankfully, the environment holds vast amounts of energy. And of typical sources like light, motion, temperature, and radiation, sunlight produces the highest power density, but only when available. Combining photovoltaic (PV) cells with tiny batteries or capacitors can therefore be more compact, reliable, and longer lasting than any one of these technologies alone. Managing a hybrid system of this sort to supply a milliwatt application, however, requires an intelligent, low-loss charger-supply system. This talk surveys and describes how smart PV-sourced microsystems can draw power from tiny PV cells and supplementary power from small batteries to supply a load and replenish the battery with excess PV power. To that end, the material reviews and discusses miniaturized PV cells, power-efficient charger-supply circuits, and reliable feedback controllers. The presentation ends with measurement results from a prototyped example.
{"title":"Tutorial: Tiny light-harvesting photovoltaic charger-supplies","authors":"G. Rincón-Mora","doi":"10.1109/ISLPED.2017.8009152","DOIUrl":"https://doi.org/10.1109/ISLPED.2017.8009152","url":null,"abstract":"A fundamental challenge wireless microsystems face is size, and in consequence, lifetime because tiny batteries exhaust quickly. Although small fuel cells and atomic sources store more energy than lithium-ion batteries and super capacitors, they source less power, so they cannot power as many functions. Small batteries and capacitors, however, cannot sustain life for long. Thankfully, the environment holds vast amounts of energy. And of typical sources like light, motion, temperature, and radiation, sunlight produces the highest power density, but only when available. Combining photovoltaic (PV) cells with tiny batteries or capacitors can therefore be more compact, reliable, and longer lasting than any one of these technologies alone. Managing a hybrid system of this sort to supply a milliwatt application, however, requires an intelligent, low-loss charger-supply system. This talk surveys and describes how smart PV-sourced microsystems can draw power from tiny PV cells and supplementary power from small batteries to supply a load and replenish the battery with excess PV power. To that end, the material reviews and discusses miniaturized PV cells, power-efficient charger-supply circuits, and reliable feedback controllers. The presentation ends with measurement results from a prototyped example.","PeriodicalId":385714,"journal":{"name":"2017 IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2017-07-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120901338","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-07-24DOI: 10.1109/ISLPED.2017.8009154
V. Nautiyal, G. Singla, Satinderjit Singh, F. Bohra, J. Dasani, Lalita Gupta, S. Dwivedi
A recent trend in the electronics industry is the concept of intelligent wearables and the Internet of Things (IoT) such as smart watches, fitness trackers, smart sensors, and smart glasses. Low power consumption is a requirement of the processors and the increasingly large embedded SRAMs in such devices. Lowering the operating voltage of these devices makes them low power. However, process variation at lower voltages causes read and write reliability issues in SRAM bitcells. To overcome issues in SRAM reliability, we present a novel, integrated read and write assist scheme with area and power savings as compared to existing state of the art schemes. For write assist, we inject negative bitline bias to raise the gate to source voltage of the bitcell access transistor, improving write margin. For read assist, we lower bitline precharge levels by adding one transistor per bitline column. Area and power savings come from capacitance sharing between the read and write assist circuitry and by precharging bitlines using recycled charged. In our SRAM implementation of the proposed circuit, we found as high as 10% dynamic power savings during bitline precharging. Using negative bitline techniques further reduced power consumption through an approximately 150mV reduction in operating voltage. Depending on the read and write margin requirements, capacitors in the design can be programmable and isolated for flexibility. The SRAM array presented in this paper also utilizes a variety of leakage reduction modes. In terms of area, for a 16384×72m8fb8 memory instance, the area overhead was only 1.7%. SRAMs using the low power, low area overhead assist scheme and the leakage reduction modes can have significant applications in wearable electronics and IoT.
{"title":"Charge recycled low power SRAM with integrated write and read assist, for wearable electronics, designed in 7nm FinFET","authors":"V. Nautiyal, G. Singla, Satinderjit Singh, F. Bohra, J. Dasani, Lalita Gupta, S. Dwivedi","doi":"10.1109/ISLPED.2017.8009154","DOIUrl":"https://doi.org/10.1109/ISLPED.2017.8009154","url":null,"abstract":"A recent trend in the electronics industry is the concept of intelligent wearables and the Internet of Things (IoT) such as smart watches, fitness trackers, smart sensors, and smart glasses. Low power consumption is a requirement of the processors and the increasingly large embedded SRAMs in such devices. Lowering the operating voltage of these devices makes them low power. However, process variation at lower voltages causes read and write reliability issues in SRAM bitcells. To overcome issues in SRAM reliability, we present a novel, integrated read and write assist scheme with area and power savings as compared to existing state of the art schemes. For write assist, we inject negative bitline bias to raise the gate to source voltage of the bitcell access transistor, improving write margin. For read assist, we lower bitline precharge levels by adding one transistor per bitline column. Area and power savings come from capacitance sharing between the read and write assist circuitry and by precharging bitlines using recycled charged. In our SRAM implementation of the proposed circuit, we found as high as 10% dynamic power savings during bitline precharging. Using negative bitline techniques further reduced power consumption through an approximately 150mV reduction in operating voltage. Depending on the read and write margin requirements, capacitors in the design can be programmable and isolated for flexibility. The SRAM array presented in this paper also utilizes a variety of leakage reduction modes. In terms of area, for a 16384×72m8fb8 memory instance, the area overhead was only 1.7%. SRAMs using the low power, low area overhead assist scheme and the leakage reduction modes can have significant applications in wearable electronics and IoT.","PeriodicalId":385714,"journal":{"name":"2017 IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2017-07-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129697636","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-07-24DOI: 10.1109/ISLPED.2017.8009169
S. Kim, Doyun Kim, Mingoo Seok
We optimize and compare the performance of synchronous and asynchronous comparators across near-threshold and nominal supply voltage (0.5∼1V). Comparators are the key components that determine the fundamental performance of analog-to-digital conversion in control and digital-signal processing (DSP) systems. While the asynchronous comparator has been considered inferior, operation of transistors in the near-threshold regime grants asynchronous comparators opportunities to improve power efficiency due to the more reduction in crowbar current than saturation drain current. We propose an enhanced asynchronous CSDA based comparator capable of achieving a superior latency vs. quiescent power dissipation trade-off to the synchronous clocked comparator in the near-threshold regime, a metric that is beneficial particularly to event-driven control systems. In-depth optimization and comparison results are presented.
{"title":"Comparative study and optimization of synchronous and asynchronous comparators at near-threshold voltages","authors":"S. Kim, Doyun Kim, Mingoo Seok","doi":"10.1109/ISLPED.2017.8009169","DOIUrl":"https://doi.org/10.1109/ISLPED.2017.8009169","url":null,"abstract":"We optimize and compare the performance of synchronous and asynchronous comparators across near-threshold and nominal supply voltage (0.5∼1V). Comparators are the key components that determine the fundamental performance of analog-to-digital conversion in control and digital-signal processing (DSP) systems. While the asynchronous comparator has been considered inferior, operation of transistors in the near-threshold regime grants asynchronous comparators opportunities to improve power efficiency due to the more reduction in crowbar current than saturation drain current. We propose an enhanced asynchronous CSDA based comparator capable of achieving a superior latency vs. quiescent power dissipation trade-off to the synchronous clocked comparator in the near-threshold regime, a metric that is beneficial particularly to event-driven control systems. In-depth optimization and comparison results are presented.","PeriodicalId":385714,"journal":{"name":"2017 IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2017-07-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126244902","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-07-24DOI: 10.1109/ISLPED.2017.8009163
Lei Jiang, Minje Kim, Wujie Wen, Danghui Wang
It is challenging to adopt computing-intensive and parameter-rich Convolutional Neural Networks (CNNs) in mobile devices due to limited hardware resources and low power budgets. To support multiple concurrently running applications, one mobile device needs to perform multiple CNN tests simultaneously in real-time. Previous solutions cannot guarantee a high enough frame rate when serving multiple applications with reasonable hardware and power cost. In this paper, we present a novel process-in-memory architecture to process emerging binary CNN tests in Wide-IO2 DRAMs. Compared to state-of-the-art accelerators, our design improves CNN test performance by 4× ∼ 11× with small hardware and power overhead.
{"title":"XNOR-POP: A processing-in-memory architecture for binary Convolutional Neural Networks in Wide-IO2 DRAMs","authors":"Lei Jiang, Minje Kim, Wujie Wen, Danghui Wang","doi":"10.1109/ISLPED.2017.8009163","DOIUrl":"https://doi.org/10.1109/ISLPED.2017.8009163","url":null,"abstract":"It is challenging to adopt computing-intensive and parameter-rich Convolutional Neural Networks (CNNs) in mobile devices due to limited hardware resources and low power budgets. To support multiple concurrently running applications, one mobile device needs to perform multiple CNN tests simultaneously in real-time. Previous solutions cannot guarantee a high enough frame rate when serving multiple applications with reasonable hardware and power cost. In this paper, we present a novel process-in-memory architecture to process emerging binary CNN tests in Wide-IO2 DRAMs. Compared to state-of-the-art accelerators, our design improves CNN test performance by 4× ∼ 11× with small hardware and power overhead.","PeriodicalId":385714,"journal":{"name":"2017 IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2017-07-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132516465","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-07-24DOI: 10.1109/ISLPED.2017.8009156
Aporva Amarnath, Siying Feng, S. Pal, T. Ajayi, A. Rovinski, R. Dreslinski
With silicon-based transistors approaching their scaling limits, multiple successor technologies are competing for silicon's place. Due to recent fabrication breakthroughs, one promising alternative is the carbon nanotube field-effect transistor (CNTFET), which uses carbon nanotubes as the channel medium instead of silicon. Although logic gates using CNTFETs have been demonstrated to provide up to an order of magnitude better energy-delay product (EDP) over silicon-based counterparts, system-level design using CNTFETs show significantly smaller EDP improvement because of the critical path of the design, output load capacitance and corresponding drive strengths of gates. In this paper, we address this challenge by exploring various architectural design choices using CNTFET-based pass transistor logic (PTL) and create an energy-efficient RISC-V processor. While silicon-based design traditionally prefers complementary logic over PTL, CNTFETs are ideal candidates for PTL due to their low threshold voltage, low power dissipation, and equal strength p-type and n-type transistors. By utilizing PTL to design modules that lie on the processor's critical path, systems can efficiently exploit CNTFET's potential benefits. Our results show that while a CNTFET RISC-V processor using complementary logic achieves a 2.9× EDP improvement over a silicon design, using PTL along the critical path components in the ALU can boost EDP improvement 5× as well as reduce area by 17% over 16 nm silicon CMOS.
{"title":"A carbon nanotube transistor based RISC-V processor using pass transistor logic","authors":"Aporva Amarnath, Siying Feng, S. Pal, T. Ajayi, A. Rovinski, R. Dreslinski","doi":"10.1109/ISLPED.2017.8009156","DOIUrl":"https://doi.org/10.1109/ISLPED.2017.8009156","url":null,"abstract":"With silicon-based transistors approaching their scaling limits, multiple successor technologies are competing for silicon's place. Due to recent fabrication breakthroughs, one promising alternative is the carbon nanotube field-effect transistor (CNTFET), which uses carbon nanotubes as the channel medium instead of silicon. Although logic gates using CNTFETs have been demonstrated to provide up to an order of magnitude better energy-delay product (EDP) over silicon-based counterparts, system-level design using CNTFETs show significantly smaller EDP improvement because of the critical path of the design, output load capacitance and corresponding drive strengths of gates. In this paper, we address this challenge by exploring various architectural design choices using CNTFET-based pass transistor logic (PTL) and create an energy-efficient RISC-V processor. While silicon-based design traditionally prefers complementary logic over PTL, CNTFETs are ideal candidates for PTL due to their low threshold voltage, low power dissipation, and equal strength p-type and n-type transistors. By utilizing PTL to design modules that lie on the processor's critical path, systems can efficiently exploit CNTFET's potential benefits. Our results show that while a CNTFET RISC-V processor using complementary logic achieves a 2.9× EDP improvement over a silicon design, using PTL along the critical path components in the ALU can boost EDP improvement 5× as well as reduce area by 17% over 16 nm silicon CMOS.","PeriodicalId":385714,"journal":{"name":"2017 IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2017-07-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124174458","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-07-24DOI: 10.1109/ISLPED.2017.8009158
Michael Mishkin, N. Kim, Mikko H. Lipasti
Dynamic power consumption associated with signal toggles over long distance wires accounts for a significant portion of on-chip interconnect power. Improving dynamic energy efficiency in highly capacitive interconnects can be achieved by reducing the toggle rates associated with data communication. Temporal coding schemes facilitate bounded activity factors by encoding information as placement of signal toggles in time and can thereby improve the energy efficiency of data communication by encoding multiple bits per toggle. We introduce two temporal protocol variants designed for traversal of the crossbars in on-chip networks. These protocols reduce peak power without loss of bandwidth and achieve energy efficient on-chip communication in high capacitance long distance interconnects. Extending these energy savings to a multi-hop mesh topology is achieved by router implementations equipped with bypassing mechanisms that elide per hop reencoding overheads. We demonstrate a four bit per transition temporal protocol with up to 75% communication energy reduction that can be achieved over a baseline serial bit stream protocol.
{"title":"Temporal codes in on-chip interconnects","authors":"Michael Mishkin, N. Kim, Mikko H. Lipasti","doi":"10.1109/ISLPED.2017.8009158","DOIUrl":"https://doi.org/10.1109/ISLPED.2017.8009158","url":null,"abstract":"Dynamic power consumption associated with signal toggles over long distance wires accounts for a significant portion of on-chip interconnect power. Improving dynamic energy efficiency in highly capacitive interconnects can be achieved by reducing the toggle rates associated with data communication. Temporal coding schemes facilitate bounded activity factors by encoding information as placement of signal toggles in time and can thereby improve the energy efficiency of data communication by encoding multiple bits per toggle. We introduce two temporal protocol variants designed for traversal of the crossbars in on-chip networks. These protocols reduce peak power without loss of bandwidth and achieve energy efficient on-chip communication in high capacitance long distance interconnects. Extending these energy savings to a multi-hop mesh topology is achieved by router implementations equipped with bypassing mechanisms that elide per hop reencoding overheads. We demonstrate a four bit per transition temporal protocol with up to 75% communication energy reduction that can be achieved over a baseline serial bit stream protocol.","PeriodicalId":385714,"journal":{"name":"2017 IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2017-07-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130950925","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-07-24DOI: 10.1109/ISLPED.2017.8009157
J. Kong, Young-Ho Gong, S. Chung
In this paper, we architect large-scale SRAM arrays with monolithic 3D (M3D) integration technology. We introduce M3D-based SRAM arrays with three different ways of integration: M3D-R (vertical routing-only), M3D-VBL (vertical bitline), and M3D-VWL (vertical wordline). We also apply M3D-based SRAM arrays to last-level caches: tag arrays for eDRAM LLCs and data arrays for SRAM LLCs. The proposed LLCs with M3D-based SRAM arrays lead to better performance and lower energy by 0.02%∼1.7% and 49.1%∼79.1%, respectively, compared to that with TSV-based 3D SRAM arrays.
{"title":"Architecting large-scale SRAM arrays with monolithic 3D integration","authors":"J. Kong, Young-Ho Gong, S. Chung","doi":"10.1109/ISLPED.2017.8009157","DOIUrl":"https://doi.org/10.1109/ISLPED.2017.8009157","url":null,"abstract":"In this paper, we architect large-scale SRAM arrays with monolithic 3D (M3D) integration technology. We introduce M3D-based SRAM arrays with three different ways of integration: M3D-R (vertical routing-only), M3D-VBL (vertical bitline), and M3D-VWL (vertical wordline). We also apply M3D-based SRAM arrays to last-level caches: tag arrays for eDRAM LLCs and data arrays for SRAM LLCs. The proposed LLCs with M3D-based SRAM arrays lead to better performance and lower energy by 0.02%∼1.7% and 49.1%∼79.1%, respectively, compared to that with TSV-based 3D SRAM arrays.","PeriodicalId":385714,"journal":{"name":"2017 IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2017-07-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125004881","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-07-24DOI: 10.1109/ISLPED.2017.8009192
Muqing Liu, Chen Zhou, Qianying Tang, K. Parhi, C. Kim
The start-up value of an SRAM cell is unique, random, and unclonable as it is determined by the inherent process mismatch between transistors. These properties make SRAM an attractive circuit for generating encryption keys. The primary challenge for SRAM based key generation, however, is the poor stability when the circuit is subject to random noise, temperature and voltage changes, and device aging. Temporal majority voting (TMV) and bit masking were used in previous works to identify and store the location of unstable or marginally stable SRAM cells. However, TMV requires a long test time and significant hardware resources. In addition, the number of repetitive power-ups required to find the most stable cells is prohibitively high. To overcome the shortcomings of TMV, we propose a novel data remanence based technique to detect SRAM cells with the highest stability for reliable key generation. This approach requires only two remanence tests: writing ‘1’ (or ‘0’) to the entire array and momentarily shutting down the power until a few cells flip. We exploit the fact that the cells that are easily flipped are the most robust cells when written with the opposite data. The proposed method is more effective in finding the most stable cells in a large SRAM array than a TMV scheme with 1,000 power-up tests. Experimental studies show that the 256-bit key generated from a 512 kbit SRAM using the proposed data remanence method is 100% stable under different temperatures, power ramp up times, and device aging.
{"title":"A data remanence based approach to generate 100% stable keys from an SRAM physical unclonable function","authors":"Muqing Liu, Chen Zhou, Qianying Tang, K. Parhi, C. Kim","doi":"10.1109/ISLPED.2017.8009192","DOIUrl":"https://doi.org/10.1109/ISLPED.2017.8009192","url":null,"abstract":"The start-up value of an SRAM cell is unique, random, and unclonable as it is determined by the inherent process mismatch between transistors. These properties make SRAM an attractive circuit for generating encryption keys. The primary challenge for SRAM based key generation, however, is the poor stability when the circuit is subject to random noise, temperature and voltage changes, and device aging. Temporal majority voting (TMV) and bit masking were used in previous works to identify and store the location of unstable or marginally stable SRAM cells. However, TMV requires a long test time and significant hardware resources. In addition, the number of repetitive power-ups required to find the most stable cells is prohibitively high. To overcome the shortcomings of TMV, we propose a novel data remanence based technique to detect SRAM cells with the highest stability for reliable key generation. This approach requires only two remanence tests: writing ‘1’ (or ‘0’) to the entire array and momentarily shutting down the power until a few cells flip. We exploit the fact that the cells that are easily flipped are the most robust cells when written with the opposite data. The proposed method is more effective in finding the most stable cells in a large SRAM array than a TMV scheme with 1,000 power-up tests. Experimental studies show that the 256-bit key generated from a 512 kbit SRAM using the proposed data remanence method is 100% stable under different temperatures, power ramp up times, and device aging.","PeriodicalId":385714,"journal":{"name":"2017 IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2017-07-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133094486","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-07-24DOI: 10.1109/ISLPED.2017.8009201
Chao Zhang, Xiaochen Guo
DRAM contributes a significant part of the total system energy consumption, and row activation is one of the most energy inefficient components. Prior works on fine-grained DRAM activation rely on increasing the number of local wires to avoid degrading performance, which adds area overheads. This work proposes interleaved I/O to allow data transferring from different partially activated banks to share the global I/O. The proposed DRAM architecture allows half-, quarter-, or one-eighth- page activations without changing the wires. The system performance is competitive as compared with other fine-grained activation designs. For the evaluated benchmarks, an average of up to 15.7% performance improvement is achieved among all of the configurations. Furthermore, the total DRAM energy can be reduced by an average of 11.2% for halfpage, 17.2% for quarterpage, and 22.3% for one-eighth-page.
{"title":"Enabling efficient fine-grained DRAM activations with interleaved I/O","authors":"Chao Zhang, Xiaochen Guo","doi":"10.1109/ISLPED.2017.8009201","DOIUrl":"https://doi.org/10.1109/ISLPED.2017.8009201","url":null,"abstract":"DRAM contributes a significant part of the total system energy consumption, and row activation is one of the most energy inefficient components. Prior works on fine-grained DRAM activation rely on increasing the number of local wires to avoid degrading performance, which adds area overheads. This work proposes interleaved I/O to allow data transferring from different partially activated banks to share the global I/O. The proposed DRAM architecture allows half-, quarter-, or one-eighth- page activations without changing the wires. The system performance is competitive as compared with other fine-grained activation designs. For the evaluated benchmarks, an average of up to 15.7% performance improvement is achieved among all of the configurations. Furthermore, the total DRAM energy can be reduced by an average of 11.2% for halfpage, 17.2% for quarterpage, and 22.3% for one-eighth-page.","PeriodicalId":385714,"journal":{"name":"2017 IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2017-07-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129522706","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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