A 900-MHz CMOS Direct Conversion Receiver

This paper describes the design of a single-chip 900-MHz CMOS direct conversion receiver (DCR) fabricated in a digital 0.6-pm technology and operating from a 3-V supply. Shown in Fig. 1 is the DCR architecture, consisting of a low-noise amplifier (LNA), quadrature mixers, simple low-pass filters (LPFs), a local oscillator (LO), a divide-by-two circuit, and baseband amplifiers, A1. An important goal in the design has been to achieve a relatively high gain (approximately 35 dB) in the RF section so as to minimize the effect of the l/f noise contributed by the baseband amplifiers. For this reason, passive mixers have been avoided even though they provide potentially higher linearity than do their active counterparts. Another goal has been to include the LO on the chip so as to obtain a realistic estimate of the leakage to the front end. The design incorporates on-chip inductors extensively to improve the performance. Fig. 2 shows the implementation of the LNA and the quadrature mixers. The LNA is configured as a cascode stage, M1 and Mz, with a 10-nH inductive load [l]. Providing high isolation between the output and the input, the cascode transistor not only improves the stability of the circuit but suppresses the LO leakage to the antenna as well. Utilizing large devices [(W/L)l = 2000 pm/0.6 pm)] and a relatively high bias current (= 5 mA), the LNA achieves a noise figure of less than 2 dB and a voltage gain of approximately 20 dB. The inductive load provides a high gain while consuming negligible voltage headroom. The use of an inductive load in the LNA prohibits the use of feedback to define the bias current and the output dc voltage of the circuit. While M3 and Ib determine the bias current, the output voltage remains close to VDD, a serious problem with respect to the bias point of thefollowing stage-the mixer. This issue is resolved as explained below. The mixer employs a single-balanced topology consisting of an input transistor M4 and a switching pair &f5-M6. In order to improve the linearity of the voltage-to-current conversion performed by the input stage, capacitor C1 degenerates transistor M4 at 900 MHz [2]. The current source defines the bias condition of M4 with little dependence on its gate voltage. The problem of noise differentiation [2] is overcome by allowing Lz and the bottom-plate parasitic capacitance of C2 (C,) to resonate in the vicinity of 900 MHz and shunt the noise current at higher harmonics of this frequency. Capacitor C2 provides ac coupling, relaxing the limited voltage headrooom issues in the switching stage and also suppressing low-frequency beat signals that are generated if two input interferers experience even-order distortion in M I , M2, and M4. Even without the voltage headroom loss that would otherwise accompany M4 in a simple mixer, the switching stage in Fig. 2 entails a number of trade-offs. To achieve a high conversion gain, M5 and M6 must remain in saturation and, more importantly, the voltage drop across R1 and R2 must be maximized. On the other hand, to minimize the noise current of M7, the allowable drain-source voltage of this device must be as large as possible. In this design, the noise current of M7 is suppressed in the band of interest (and higher harmonics thereof) through the use of the degenerating inductor L3. This technique makes it possible to choose VDS7 M 0.5 V with negligible noise penalty, thereby allowing a large voltage drop across R1 and R2. The output nodes of the mixer are loaded with on-chip capacitors to suppress high-frequency components, but channelselection filtering is not included here. Fig. 3 illustrates the LO and the divide-by-twocircuit. Using a cross-coupled pair Ml-M2 and 10-nH inductors L1 and L2, the oscillator operates at 1.8 GHz while directly driving the divider. The latter is configured as a master-slave flipflop driven differentially through M3-M4 and M5-M6. Proper sizing of the devices in each latch provides division speeds in excess of 2 GHz even with the r latively heavy capacitive loading imposed by the switching pairs in the quadrature mixers. Resistors R5 and Rg shift the high level of ILO and &LO down to avoid driving the mixer switching pairs into the triode region. The downconverted signal can be further processed by one of the three permutations depicted in Fig. 4 [3] . In Fig. 4(a), a low-pass filter suppresses out-of-channel interferers, allowing A1 to be a nonlinear, high-gain amplifier and the analog-todigital converter (ADC) to have a moderate dynamic range. (roughly 4 to 8 bits depending on the gain control in the RF domain and the type of modulation). However, the low-pass filter design entails severe noise-linearity-power tradeoffs. The second permutation, shown in Figure 4(b), relaxes the LPF noise requirements while demanding a higher performance in the amplifier. The difficulty here is that the signals are still quite small and the interferers quite large. Thus, AI must exhibit both low noise and high linearity. The present design is intended for permutations in Figs. 4(b) and (c). Shown in Fig. 5 is the implementation of the baseband amplifier, consisting of a degenerated differential pair M I -M2 and load devices R1-R2 and M3-M4. Since high linearity requires a large Is Rs, the maximum voltage gain with a 3-V supply is quite limited. To resolve this issue, the PMOS current sources have been added so as to provide about 75% of the drain current of M I and M2, thereby allowing a large value for R1 and R2 and hence a high gain in the stage. The linearity of the baseband amplifier is limited by both the nonlinear characteristics of M1-M2 and the nonlinear output impedance of M3-M4, even though all the transistors are in saturation. For this reason, the length of M3-M4 has been increased to 4 pm. To reduce the l/f noise, wide transistors have been used: W1,2 = 2000 pm, W 3 , 4 = 1600 pm. The complete receiver has been fabricated in a 0.6-pm digital CMOS technology. The inductors are implemented as a stack of two spiral structures made of the second and third metal layers