Alessio Boggiano, Simone Delfitto, Tomaso Poggi, M. Storace
{"title":"一种新的FPGA实现方案,用于电路实现PWL功能","authors":"Alessio Boggiano, Simone Delfitto, Tomaso Poggi, M. Storace","doi":"10.1109/ECCTD.2007.4529736","DOIUrl":null,"url":null,"abstract":"A new scheme for the circuit realization of multivariate PWL functions is proposed. A three-variate version is implemented on an FPGA board. A comparison with respect to another scheme, already implemented on chip, is provided, showing that the new scheme is more complex, but reduces the computation times. Two benchmark examples are considered to show the high accuracy of the circuit in the representation of PWL functions.","PeriodicalId":445822,"journal":{"name":"2007 18th European Conference on Circuit Theory and Design","volume":"17 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2007-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"9","resultStr":"{\"title\":\"FPGA implementation of a new scheme for the circuit realization of PWL functions\",\"authors\":\"Alessio Boggiano, Simone Delfitto, Tomaso Poggi, M. Storace\",\"doi\":\"10.1109/ECCTD.2007.4529736\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A new scheme for the circuit realization of multivariate PWL functions is proposed. A three-variate version is implemented on an FPGA board. A comparison with respect to another scheme, already implemented on chip, is provided, showing that the new scheme is more complex, but reduces the computation times. Two benchmark examples are considered to show the high accuracy of the circuit in the representation of PWL functions.\",\"PeriodicalId\":445822,\"journal\":{\"name\":\"2007 18th European Conference on Circuit Theory and Design\",\"volume\":\"17 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2007-08-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"9\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"2007 18th European Conference on Circuit Theory and Design\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ECCTD.2007.4529736\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"2007 18th European Conference on Circuit Theory and Design","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ECCTD.2007.4529736","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
FPGA implementation of a new scheme for the circuit realization of PWL functions
A new scheme for the circuit realization of multivariate PWL functions is proposed. A three-variate version is implemented on an FPGA board. A comparison with respect to another scheme, already implemented on chip, is provided, showing that the new scheme is more complex, but reduces the computation times. Two benchmark examples are considered to show the high accuracy of the circuit in the representation of PWL functions.